MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 222

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.6.1 FCSM Counter
10.6.2 FCSM Clock Sources
10.6.3 FCSM External Event Counting
10.6.4 FCSM Time Base Bus Driver
10.6.5 FCSM Interrupts
10-6
MOTOROLA
The FCSM counter consists of a 16-bit register and a 16-bit up-counter. Reading the
register transfers the contents of the counter to the data bus, while a write to the
register loads the counter with a new value. Overflow of the counter is defined to be
the transition from $FFFF to $0000. An overflow condition sets the counter overflow
flag (COF) in the FCSM status/interrupt/control register (FCSMSIC).
The FCSM has eight software selectable counter clock sources, including:
The clock source is selected by the CLK[2:0] bits in FCSMSIC. When the CLK[2:0] bits
are being changed, internal circuitry guarantees that spurious edges occurring on the
CTM2C pin do not affect the FCSM. The read-only IN bit in FCSMSIC reflects the state
of CTM2C. This pin is Schmitt-triggered and is synchronized with the system clock.
The maximum allowable frequency for a clock input on CTM2C is f
When an external clock source is selected, the FCSM can act as an event counter
simply by counting the number of events occurring on the CTM2C input pin. Alterna-
tively, the FCSM can be programmed to generate an interrupt request when a pre-
defined number of events have been counted. This is done by presetting the counter
with the two’s complement value of the desired number of events.
The DRVA and DRVB bits in FCSMSIC select the time base bus to be driven. Which
of the time base buses is driven depends on where the FCSM is physically placed in
any particular CTM implementation. Refer to Figure 10-1 and Table 10-1 for more
information.
The FCSM can optionally request an interrupt when its counter overflows and the COF
bit in FCSMSIC is set. To enable interrupts, set the IL[2:0] field in the FCSMSIC to a
non-zero value. The CTM4 compares the CPU32 IP mask value to the priority of the
requested interrupt designated by IL[2:0] to determine whether it should contend for
• Six CPSM prescaler outputs (PCLK[1:6])
• Rising edge on CTM2C input
• Falling edge on the CTM2C input
Reset presets the counter register to $0000. Writing $0000 to the
counter register while the counter’s value is $FFFF does not set the
COF flag and does not generate an interrupt request.
Two time base buses should not be driven at the same time.
CONFIGURABLE TIMER MODULE 4
WARNING
NOTE
sys
/4.
USER’S MANUAL
MC68336/376