MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 112

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.6.4.2 LPSTOP Broadcast Cycle
5.6.5 Bus Exception Control Cycles
5-34
MOTOROLA
Low-power stop mode is initiated by the CPU32. Individual modules can be stopped
by setting the STOP bits in each module configuration register, or the SIM can turn off
system clocks after execution of the LPSTOP instruction. When the CPU32 executes
LPSTOP, an LPSTOP broadcast cycle is generated. The SIM brings the MCU out of
low-power stop mode when either an interrupt of higher priority than the stored mask
or a reset occurs. Refer to 5.3.4 Low-Power Operation and 4.8.2.1 Low-Power Stop
(LPSTOP) for more information.
During an LPSTOP broadcast cycle, the CPU32 performs a CPU space write to ad-
dress $3FFFE. This write puts a copy of the interrupt mask value in the clock control
logic. The mask is encoded on the data bus as shown in Figure 5-14. The LPSTOP
CPU space cycle is shown externally (if the bus is available) as an indication to exter-
nal devices that the MCU is going into low-power stop mode. The SIM provides an in-
ternally generated DSACK response to this cycle. The timing of this bus cycle is the
same as for a fast termination write cycle. If the bus is not available (arbitrated away),
the LPSTOP broadcast cycle is not shown externally.
An external device or a chip-select circuit must assert at least one of the DSACK[1:0]
signals or the AVEC signal to terminate a bus cycle normally. Bus error processing oc-
curs when bus cycles are not terminated in the expected manner. The SIM bus monitor
can be used to generate BERR internally, causing a bus error exception to be taken.
Bus cycles can also be terminated by assertion of the external BERR or HALT pins
signal, or by assertion of the two signals simultaneously.
Acceptable bus cycle termination sequences are summarized as follows. The case
numbers refer to Table 5-13, which indicates the results of each type of bus cycle ter-
mination.
• Normal Termination
• Halt Termination
— DSACK is asserted; BERR and HALT remain negated (case 1).
— HALT is asserted at the same time or before DSACK, and BERR remains
negated (case 2).
BERR during the LPSTOP broadcast cycle is ignored.
15
0
14
0
Figure 5-14 LPSTOP Interrupt Mask Level
13
0
12
0
SYSTEM INTEGRATION MODULE
11
0
10
0
9
0
8
0
NOTE
7
0
6
0
5
0
4
0
3
0
2
IP MASK
1
LPSTOP MASK LEVEL
0
USER’S MANUAL
MC68336/376