MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 203

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

MC68336/376
USER’S MANUAL
• Software initiated single-scan mode
• External trigger rising or falling edge single-scan mode
• Interval timer single-scan mode
— Software can initiate the execution of a scan sequence for queue 1 or 2 by
— The QADC automatically performs the conversions in the queue until an end-
— This mode is a variation of the external trigger continuous-scan mode. It is
— In addition to the above modes, queue 2 can also be programmed for the in-
— When this mode is selected and software sets the single-scan enable bit in
— The QADC automatically performs the conversions in the queue until a pause
— Software may set the single-scan enable bit again, allowing another scan of
selecting this mode, and setting the single-scan enable bit in QACR1 or
QACR2. A trigger event is generated internally and the QADC immediately
begins execution of the first CCW in the queue. If a pause is encountered,
queue execution ceases momentarily while another trigger event is generated
internally, and then execution continues. While the time to internally generate
and act on a trigger event is very short, software can momentarily read the sta-
tus conditions, indicating that the queue is paused.
of-queue condition is encountered. The queue remains idle until software
again sets the single-scan enable bit. The trigger overrun flag is never set
while in this mode.
available for both queue 1 and queue 2. Software programs the external
trigger to be either a rising or a falling edge. Software must also set the single-
scan enable bit for the queue in order for the scan to take place. The first ex-
ternal trigger edge causes the queue to be executed one time. Each CCW is
read and the indicated conversions are performed until an end-of-queue con-
dition is encountered. After the queue scan is complete, the QADC clears the
single-scan enable bit. Software may set the single-scan enable bit again to
allow another scan of the queue to be initiated by the next external trigger
edge.
terval timer single-scan mode. The queue operating mode for queue 2 is se-
lected by the MQ2 field in QACR2.
QACR2, the periodic/interval timer begins counting. The timer interval can
range from 2
expires, a trigger event is generated internally to start the queue. The timer is
reloaded and begins counting again. Meanwhile, the QADC begins execution
with the first CCW in queue 2.
or an end-of-queue condition is encountered. When a pause is encountered,
queue execution stops until the timer interval expires again; queue execution
then continues. When an end of queue condition is encountered, the timer is
held in reset and the single-scan enable bit is cleared.
the queue to be initiated by the interval timer. The interval timer generates a
trigger event whenever the time interval elapses. The trigger event may cause
queue execution to continue following a pause, or may be considered a trigger
overrun if the queue is currently executing.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
7
to 2
17
QCLK cycles in binary multiples. When the time interval
MOTOROLA
8-21