MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 207

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

MC68336/376
USER’S MANUAL
To accommodate wide variations of the main MCU clock frequency f
generated by a programmable prescaler which divides the MCU system clock to a
frequency within the specified QCLK tolerance range. The prescaler also allows the
duty cycle of the QCLK waveform to be programmable.
The basic high phase of the QCLK waveform is selected with the PSH (prescaler clock
high time) field in QACR0, and the basic low phase of QCLK with the PSL (prescaler
clock low time) field. The duty cycle of QCLK can be further modified with the PSA
(prescaler add a clock tick) bit in QACR0. The combination of the PSH and PSL pa-
rameters establishes the frequency of QCLK.
Figure 8-8 shows that the prescaler is essentially a variable pulse width signal gener-
ator. A 5-bit down counter, clocked at the system clock rate, is used to create both the
high phase and the low phase of the QCLK signal. At the beginning of the high phase,
the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that
the high phase is finished, QCLK is reset. A 3-bit comparator looks for a one’s com-
plement match with the 3-bit PSL value, which is the end of the low phase of QCLK.
The PSA bit allows the QCLK high-to-low transition to be delayed by a half cycle of the
input clock.
The following sequence summarizes the process of determining what values are to be
put into the prescaler fields in QACR0:
1. Choose the system clock frequency f
2. Choose first-try values for PSH, PSL, and PSA, then skip to step 4.
3. Choose different values for PSH, PSL, and PSA.
4. If the QCLK high time is less than t
5. If QCLK low time is less than t
phase time), return to step 3. Refer to Table A-13 for more information on t
QCLK high time is determined by the following equation:
where PSH = 0 to 31 and PSA = 0 or 1.
time), return to step 3. Refer to Table A-13 for more information on t
low time is determined by the following equation:
where PSL = 0 to 7 and PSA = 0 or 1.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
QCLK high time (in ns)
QCLK low time (in ns)
PSL
(QADC clock duty cycle – Minimum low phase
PSH
=
=
sys
1000 1
-------------------------------------------------------------------- -
1000 1
--------------------------------------------------------------------- -
(QADC clock duty cycle – Minimum high
.
f
f
sys
sys
+
+
PSL 0.5 PSA
PSH
(in MHz)
(in MHz)
–
+
0.5 PSA
sys
MOTOROLA
, QCLK is
PSL
.
QCLK
8-25
PSH
.