MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 68

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4-16
MOTOROLA
All exception vectors, except the reset vector and stack pointer, are located in super-
visor data space. The reset vector and stack pointer are located in supervisor program
space. Only the initial reset vector and stack pointer are fixed in the processor memory
map. When initialization is complete, there are no fixed assignments. Since the VBR
stores the vector table base address, the table can be located anywhere in memory.
It can also be dynamically relocated for each task executed by an operating system.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are ob-
tained from an external device; others are supplied by the processor. The processor
multiplies the vector number by four to calculate vector offset, then adds the offset to
the contents of the VBR. The sum is the memory address of the vector.
Number
64–255
Vector
16–23
32–47
48–58
59–63
10
11
12
13
14
15
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
Table 4-3 Exception Vector Assignments
1020
Dec
100
104
108
112
116
120
124
128
188
192
232
236
252
256
12
16
20
24
28
32
36
40
44
48
52
56
60
64
92
96
0
4
8
CENTRAL PROCESSOR UNIT
Vector Offset
0BC
0EC
Hex
00C
01C
02C
03C
05C
06C
07C
0C0
0E8
0FC
3FC
000
004
008
010
014
018
020
024
028
030
034
038
040
060
064
068
070
074
078
080
100
Space
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SP
SP
(Reserved, coprocessor protocol violation)
Format error and uninitialized interrupt
Format error and uninitialized interrupt
Trap instruction vectors (0–15)
Reset: initial program counter
TRAPcc, TRAPV instructions
Level 1 interrupt autovector
Level 2 interrupt autovector
Level 3 interrupt autovector
Level 4 interrupt autovector
Level 5 interrupt autovector
Level 6 interrupt autovector
Level 7 interrupt autovector
User defined vectors (192)
Reset: initial stack pointer
(Reserved, coprocessor)
CHK, CHK2 instructions
(Unassigned, reserved)
(Unassigned, reserved)
Hardware breakpoint
Line 1010 emulator
Line 1111 emulator
Spurious interrupt
Privilege violation
Illegal instruction
Address error
Assignment
Zero division
Bus error
Trace
USER’S MANUAL
MC68336/376