MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 359

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

STOP — Low-Power Stop Mode Enable
FRZ1— FREEZE Assertion Response
FRZ0 — Not Implemented
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted Data Space
Bits [6:4] — Not Implemented
IARB[3:0] — Interrupt Arbitration ID
D.6.2 QSM Test Register
QTEST — QSM Test Register
D.6.3 QSM Interrupt Level Register
QILR — QSM Interrupt Levels Register
The values of ILQSPI[2:0] and ILSCI[2:0] in QILR determine the priority of QSPI and SCI
interrupt requests.
MC68336/376
USER’S MANUAL
15
0
0
RESET:
When STOP is set, the QSM enters low-power stop mode. The system clock input to
the module is disabled. While STOP is set, only QSMCR reads are guaranteed to be
valid, but writes to the QSPI RAM and other QSM registers are guaranteed valid. The
SCI receiver and transmitter must be disabled before STOP is set. To stop the QSPI,
set the HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP.
FRZ1 determines what action is taken by the QSPI when the IMB FREEZE signal is
asserted.
The SUPV bit places the QSM registers in either supervisor or user data space.
The IARB field is used to arbitrate between simultaneous interrupt requests of the
same priority. Each module that can generate interrupt requests must be assigned a
unique, non-zero IARB field value.
Used for factory test only.
0 = QSM clock operates normally.
1 = QSM clock is stopped.
0 = Ignore the IMB FREEZE signal.
1 = Halt the QSPI on a transfer boundary.
0 = Registers with access controlled by the SUPV bit are accessible in either
1 = Registers with access controlled by the SUPV bit are restricted to supervisor
14
0
0
supervisor or user mode.
access only.
13
0
ILQSPI[2:0]
12
0
11
0
10
0
ILSCI[2:0]
REGISTER SUMMARY
9
0
8
0
7
6
5
4
QIVR
3
2
$YFFC02
$YFFC04
MOTOROLA
1
D-41
0