MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 266

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.4.5 Time Stamp
13-10
MOTOROLA
Both counters are read only (except in test/freeze/halt modes).
The TouCAN responds to any bus state as described in the CAN protocol, transmitting
an error active or error passive flag, delaying its transmission start time (error passive)
and avoiding any influence on the bus when in the bus off state. The following are the
basic rules for TouCAN bus state transitions:
The value of the free-running 16-bit timer is sampled at the beginning of the identifier
field on the CAN bus. For a message being received, the time stamp will be stored in
the time stamp entry of the receive message buffer at the time the message is written
into that buffer. For a message being transmitted, the time stamp entry will be written
into the transmit message buffer once the transmission has completed successfully.
• Cascade usage of TX error counter with an additional internal counter to detect
• If the value of the TX error counter or RX error counter increments to a value
• If the TouCAN is in an error passive state, and either the TX error counter or RX
• If the value of the TX error counter increases to a value greater than 255, the
• If the TouCAN is in the bus off state, the TX error counter and an additional inter-
• If only one node is operating in a system, the TX error counter will increment with
• If the RX error counter increments to a value greater than 127, it will stop incre-
the 128 occurrences of 11 consecutive recessive bits necessary to transition from
bus off into error active.
greater than or equal to 128, the fault confinement state (FCS[1:0]) field in the
error status register is updated to reflect an error passive state.
error counter decrements to a value less than or equal to 127, while the other er-
ror counter already satisfies this condition, the FCS[1:0] field in the error status
register is updated to reflect an error active state.
FCS[1:0] field in the error status register is updated to reflect a bus off state, and
an interrupt may be issued. The value of the TX error counter is reset to zero.
nal counter are cascaded to count 128 occurrences of 11 consecutive recessive
bits on the bus. To do this, the TX error counter is first reset to zero, then the in-
ternal counter begins counting consecutive recessive bits. Each time the internal
counter counts 11 consecutive recessive bits, the TX error counter is incremented
by one and the internal counter is reset to zero. When the TX error counter reach-
es the value of 128, the FCS[1:0] field in the error status register is updated to be
error active, and both error counters are reset to zero. Any time a dominant bit is
detected following a stream of less than 11 consecutive recessive bits, the inter-
nal counter resets itself to zero, but does not affect the TX error counter value.
each message it attempts to transmit, due to the resulting acknowledgment er-
rors. However, acknowledgment errors will never cause the TouCAN to transition
from the error passive state to the bus off state.
menting, even if more errors are detected while being a receiver. After the next
successful message reception, the counter is reset to a value between 119 and
127, to enable a return to the error active state.
CAN 2.0B CONTROLLER MODULE (TouCAN)
USER’S MANUAL
MC68336/376