MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 170

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.3.5.4 Slave Wrap-Around Mode
9.3.6 Peripheral Chip Selects
9-20
MOTOROLA
Because the command RAM is not used in slave mode, the CONT, BITSE, DT, DSCK,
and peripheral chip-select bits have no effect. The PCS0/SS pin is used only as an in-
put.
The SPBR, DT and DSCKL fields in SPCR0 and SPCR1 bits are not used in slave
mode. The QSPI drives neither the clock nor the chip-select pins and thus cannot con-
trol clock rate or transfer delay.
Because the BITSE option is not available in slave mode, the BITS field in SPCR0
specifies the number of bits to be transferred for all transfers in the queue. When the
number of bits designated by BITS[3:0] has been transferred, the QSPI stores the
working queue pointer value in CPTQP, increments the working queue pointer, and
loads new transmit data from transmit RAM into the data serializer. The working queue
pointer address is used the next time PCS0/SS is asserted, unless the CPU32 writes
to NEWQP first.
The QSPI shifts one bit for each pulse of SCK until the slave select input goes high. If
SS goes high before the number of bits specified by the BITS field is transferred, the
QSPI resumes operation at the same pointer address the next time SS is asserted.
The maximum value that the BITS field can have is 16. If more than 16 bits are trans-
mitted before SS is negated, pointers are incremented and operation continues.
The QSPI transmits as many bits as it receives at each queue address, until the BITS
value is reached or SS is negated. SS does not need to go high between transfers as
the QSPI transfers data until reaching the end of the queue, whether SS remains low
or is toggled between transfers.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wrap-around mode is enabled.
Slave wrap-around mode is enabled by setting the WREN bit in SPCR2. The queue
can wrap to pointer address $0 or to the address pointed to by NEWQP, depending on
the state of the WRTO bit in SPCR2. Slave wrap-around operation is identical to mas-
ter wrap-around operation.
Peripheral chip-select signals are used to select an external device for serial data
transfer. Chip-select signals are asserted when a command in the queue is executed.
Signals are asserted at a logic level corresponding to the value of the PCS[3:0] bits in
each command byte. More than one chip-select signal can be asserted at a time, and
more than one external device can be connected to each PCS pin, provided proper
fanout is observed. PCS0 shares a pin with the slave select SS signal, which initiates
slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a
mode fault occurs.
QUEUED SERIAL MODULE
USER’S MANUAL
MC68336/376