MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 180

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MC68376BGMAB20

Manufacturer Part Number
MC68376BGMAB20
Description
IC MCU 32BIT 8K ROM 160-QFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68376BGMAB20

Core Processor
CPU32
Core Size
32-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Ram Size
7.5K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
160-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68376BGMAB20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
9.4.3.9 Internal Loop
9.5 QSM Initialization
9-30
MOTOROLA
The LOOPS bit in SCCR1 controls a feedback path in the data serial shifter. When
LOOPS is set, the SCI transmitter output is fed back into the receive serial shifter. TXD
is asserted (idle line). Both transmitter and receiver must be enabled before entering
loop mode.
After reset, the QSM remains in an idle state until initialized. A general guide for
initialization follows.
A. Global
B. Queued Serial Peripheral Interface
C. Serial Communication Interface
1. Configuration QSMCR
2. Configure QIVR and QILR
3. Configure PORTQS and DDRQS
4. Assign pin functions by writing to the pin assignment register PQSPAR
1. Write appropriate values to QSPI command RAM and transmit RAM.
2. Set up the SPCR0
3. Set up SPCR1
4. Set up SPCR2
5. Set up SPCR3
6. To enable the QSPI, set the SPE bit in SPCR1.
1. Set up SCCR0
a.Write an interrupt arbitration priority value into the IARB field.
b. Clear the FREEZE and/or STOP bits for normal operation.
a. Write QSPI/SCI interrupt vector number into QIVR.
b. Write QSPI (ILSPI) and SCI (ILSCI) interrupt priorities into QILR.
a. Write a data word to PORTQS.
b. Set the direction of QSM pins used for I/O by writing to DDRQS.
a. Set the bit in with the BR field.
b. Determine clock phase (CPHA), and clock polarity (CPOL).
c. Determine number of bits to be transferred in a serial operation
d. Select master or slave operating mode (MSTR).
e. Enable or disable wired-OR operation (WOMQ).
a. Establish a delay following serial transfer by writing to the DTL field.
b. Establish a delay before serial transfer by writing to the DSCKL field.
a. Write an initial queue pointer value into the NEWQP field.
b. Write a final queue pointer value into the ENDQP field.
c. Enable or disable queue wrap-around (WREN).
d. Set wrap-around address if enabled (WRTO).
e. Enable or disable QSPI interrupt (SPIFIE).
a. Enable or disable halt at end of queue (HALT).
b. Enable or disable halt and mode fault interrupts (HMIE).
c. Enable or disable loopback (LOOPQ).
a. Set the baud with the SCBR field.
(BITS[3:0]).
QUEUED SERIAL MODULE
USER’S MANUAL
MC68336/376

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