MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 113

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

MC68336/376
USER’S MANUAL
Table 5-13 shows various combinations of control signal sequences and the resulting
bus cycle terminations.
To control termination of a bus cycle for a retry or a bus error condition properly,
DSACK, BERR, and HALT must be asserted and negated with the rising edge of the
MCU clock. This ensures that when two signals are asserted simultaneously, the
required setup time and hold time for both of them are met for the same falling edge
of the MCU clock. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for
timing requirements. External circuitry that provides these signals must be designed
with these constraints in mind, or else the internal bus monitor must be used.
DSACK, BERR, and HALT may be negated after AS is negated.
• Bus Error Termination
• Retry Termination
Number
NOTES:
— BERR is asserted in lieu of, at the same time as, or before DSACK (case 3),
— HALT and BERR are asserted in lieu of, at the same time as, or before DSACK
Case
1. N = The number of current even bus state (S2, S4, etc.).
2. A = Signal is asserted in this bus state.
3. NA = Signal is not asserted in this state.
4. X = Don’t care.
5. S = Signal was asserted in previous state and remains asserted in this state.
1
2
3
4
5
6
or after DSACK (case 4), and HALT remains negated; BERR is negated at the
same time or after DSACK.
(case 5) or after DSACK (case 6); BERR is negated at the same time or after
DSACK; HALT may be negated at the same time or after BERR.
Control Signal
Table 5-13 DSACK, BERR, and HALT Assertion Results
DSACK
DSACK
DSACK
DSACK
DSACK
DSACK
BERR
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
HALT
SYSTEM INTEGRATION MODULE
Asserted on Rising
NA/A
NA/A
NA
A/S
A/S
Edge of State
NA
NA
NA
NA
NA
NA
N
A
A
A
A
A
A
A
2
1
3
N + 2
NA
NA
NA
S
X
S
S
X
S
X
X
S
X
S
S
X
A
A
4
5
Normal termination.
Halt termination: normal cycle terminate and halt.
Continue when HALT is negated.
Bus error termination: terminate and take bus error
exception, possibly deferred.
Bus error termination: terminate and take bus error
exception, possibly deferred.
Retry termination: terminate and retry when HALT is
negated.
Retry termination: terminate and retry when HALT is
negated.
Result
MOTOROLA
5-35