MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 406

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

CANICR — TouCAN Interrupt Configuration Register
CANCTRL0 — Control Register 0
IARB[3:0] — Interrupt Arbitration ID
D.10.2 TouCAN Test Configuration Register
CANTCR — TouCAN Test Configuration Register
D.10.3 TouCAN Interrupt Configuration Register
ILCAN[2:0] — Interrupt Request Level
IVBA[2:0] — Interrupt Vector Base Address
D.10.4 Control Register 0
D-88
MOTOROLA
BOFF
MSK
15
15
0
0
RESET:
RESET:
The IARB field is used to arbitrate between simultaneous interrupt requests of the
same priority. Each module that can generate interrupt requests must be assigned a
unique, non-zero IARB field value.
Used for factory test only.
When the TouCAN generates an interrupt request, ILCAN[2:0] determines which of
the interrupt request signals is asserted. When a request is acknowledged, the
TouCAN compares ILCAN[2:0] to a mask value supplied by the CPU32 to determine
whether to respond. ILCAN[2:0] must have a value in the range of $0 (interrupts
disabled) to $7 (highest priority).
The interrupt vector base address specifies the high-order three bits of all the vector
numbers generated by the different TouCAN interrupt sources.
ERR
MSK
0 = The TouCAN is not in low-power stop mode and its clocks are running.
1 = The TouCAN has entered low-power stop mode and its clocks are stopped
14
14
0
0
RESERVED
13
13
RESERVED
0
0
If the TouCAN issues an interrupt request after reset and before
IVBA[2:0] is initialized, it will drive $0F as the “uninitialized” interrupt
vector in response to a CPU32 interrupt acknowledge cycle, regard-
less of the specific event.
12
12
0
0
RXMODE[1:0]
11
11
0
0
10
10
0
0
ILCAN[2:0]
REGISTER SUMMARY
TXMODE[1:0]
9
0
9
0
8
0
8
0
NOTE
7
0
7
0
IVBA[2:0]
6
0
6
0
5
0
5
0
CANCTRL1
4
0
4
0
3
1
3
1
RESERVED
USER’S MANUAL
2
1
2
0
MC68336/376
$YFF084
$YFF086
$YFF082
1
1
1
0
0
1
0
0