MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 349

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

QACR0 — QADC Control Register 0
D.5.6 QADC Control Registers
MUX — Externally Multiplexed Mode
PSH[4:0] — Prescaler Clock High Time
PSA — Prescaler Add a Tick
PSL[2:0] — Prescaler Clock Low Time
MC68336/376
USER’S MANUAL
RESET:
MUX
15
0
The MUX bit configures the QADC for externally multiplexed mode, which affects the
interpretation of the channel numbers and forces the MA[2:0] pins to be outputs.
The PSH field selects the QCLK high time in the prescaler. To keep QCLK within the
specified range, PSH[4:0] must be programmed to guarantee the minimum acceptable
time for parameter t
equation relates t
The PSA bit modifies the QCLK duty cycle by adding one system clock tick to the high
time and subtracting one system clock tick from the low time.
The PSL field selects the QCLK low time in the prescaler. To keep QCLK within the
specified range, PSL[2:0] must be programmed to guarantee the minimum acceptable
time for parameter t
equation relates t
0 = Internally multiplexed, 16 possible channels.
1 = Externally multiplexed, 44 possible channels.
0 = QCLK high and low times are not modified.
1 = Add one system clock tick to the high time of QCLK and subtract one system
14
clock tick from the low time.
13
12
RESERVED
PSH
PSL
11
PSH
PSL
to PSL[2:0]:
to PSH[4:0]:
(refer to Table A-13 for more information). The following
(refer to Table A-13 for more information). The following
10
REGISTER SUMMARY
9
t
t
PSH
PSL
8
0
=
=
PSH[4:0]
-------------------------------- -
PSL[2:0]
------------------------------- -
7
0
f
f
PSH[4:0]
sys
sys
6
0
+
+
1
1
5
1
4
1
PSA
3
0
2
0
$YFF20A
MOTOROLA
PSL[2:0]
1
1
D-31
0
1