MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 419

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

CIBV D-77
CIE1 D-32
CIE2 D-33
CIER 11-15, D-77
CIRL D-77
CISR 11-13, 11-15, D-80
Clear (definition) 2-8
CLK D-60, D-62, D-70
CLKOUT 5-26, 5-41
CLKRST (clock reset) 5-41
CLKS D-75
Clock
Code 13-4
COF D-59, D-61
Coherency 8-6, 8-22, 11-4
COMM 11-12
Command
Common in-circuit emulator 4-19
Comparator 8-16
Completed queue pointer (CPTQP) D-53
Condition code register (CCR) 4-6, 11-5
CONT D-54
Contention 5-52
Continue (CONT) D-54
Continuous transfer mode 9-6
Conventions 2-8
Conversion
MC68336/376
USER’S MANUAL
pin
reset operation 5-62
signals for interrupt acknowledge 5-61
timing diagram A-18
output timing diagram A-10
block diagram 8-24
control
generation 8-24
input pin status (FCSM) D-60
input pin status (MCSM) D-62
mode
output (CLKOUT) 5-26
phase (CPHA) D-49
polarity (CPOL) D-49
rate selection (CLK) field D-70
synthesizer
RAM 9-8
word pointer (CWP) D-36
command word table (CCW) 8-1, 8-16, 8-28
cycle times 8-13
register boot ROM (CSORBT) D-18
registers (CSOR) 5-57, 5-59, D-18
assignment registers (CSPAR) 5-57, D-15
multipliers 5-8
timing (electricals) A-3
pin (MODCLK) 5-44
selection 5-44
control register (SYNCR) D-8
operation 5-5
reset values 5-63
field encoding 5-58, D-16
pin
assignments D-16
Counter
CPCR D-58
CPHA 9-16, D-49
CPOL 9-16, D-49
CPR D-79
CPSM 10-4
CPTQP 9-8, D-53
CPTR D-59
CPU
CPU32 5-40
CPU32 Reference Manual 4-1
CR D-54
CRCERR D-94
CREG D-21
stages 8-30
clock select (CLK) field
overflow flag (COF) bit D-59, D-61
prescaler submodule. See CPSM 10-4
block diagram 10-4
registers 10-5
space
address registers/address organization in 4-5
addressing modes 4-9
block diagram 4-2
data registers 4-4
development support 4-17
exception processing 4-15
features 3-1
generated message encoding 4-25
instructions 4-10
loop mode 4-15
memory organization 4-7
processing states 4-9
register
registers 4-2
virtual memory 4-9
FCSM D-60
MCSM D-62
control register (CPCR) D-58
test register (CPTR) D-59
address encoding 5-31
cycles 5-30
encoding for interrupt acknowledge 5-61
data organization 4-5
LPSTOP 4-14
MOVEC 4-7
MOVES 4-7
RESET 5-41
special control instructions 4-14
table lookup and interpolate (TBL) 4-14
umimplemented MC68020 instructions 4-10
mnemonics 2-2
model 4-3, D-2
alternate function code registers (SFC/DFC) 4-7
condition code register (CCR) 4-6, D-3
control registers 4-6
program counter (PC) 4-1
stack pointer (SP) 4-1
status register (SR) 4-6, D-3
vector base register (VBR) 4-7
MOTOROLA
I-3