MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 93

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MC68376BGMAB20

Manufacturer Part Number
MC68376BGMAB20
Description
IC MCU 32BIT 8K ROM 160-QFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68376BGMAB20

Core Processor
CPU32
Core Size
32-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Ram Size
7.5K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
160-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68376BGMAB20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
5.4.3 Halt Monitor
5.4.4 Spurious Interrupt Monitor
5.4.5 Software Watchdog
MC68336/376
USER’S MANUAL
The monitor does not check DSACK response on the external bus unless the CPU32
initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter-
nal to external bus cycles. If a system contains external bus masters, an external bus
monitor must be implemented and the internal-to-external bus monitor option must be
disabled.
When monitoring transfers to an 8-bit port, the bus monitor does not reset until both
byte accesses of a word transfer are completed. Monitor time-out period must be at
least twice the number of clocks that a single byte access requires.
The halt monitor responds to an assertion of the HALT signal on the internal bus,
caused by a double bus fault. A flag in the reset status register (RSR) indicates that
the last reset was caused by the halt monitor. Halt monitor reset can be inhibited by
the halt monitor (HME) enable bit in SYPCR. Refer to 5.6.5.2 Double Bus Faults for
more information.
During interrupt exception processing, the CPU32 normally acknowledges an interrupt
request, recognizes the highest priority source, and then either acquires a vector or
responds to a request for autovectoring. The spurious interrupt monitor asserts the in-
ternal bus error signal (BERR) if no interrupt arbitration occurs during interrupt
exception processing. The assertion of BERR causes the CPU32 to load the spurious
interrupt exception vector into the program counter. The spurious interrupt monitor
cannot be disabled. Refer to 5.8 Interrupts for more information. For detailed informa-
tion about interrupt exception processing, refer to 4.9 Exception Processing.
The software watchdog is controlled by the software watchdog enable (SWE) bit in
SYPCR. When enabled, the watchdog requires that a service sequence be written to
the software service register (SWSR) on a periodic basis. If servicing does not take
place, the watchdog times out and asserts the RESET signal.
Each time the service sequence is written, the software watchdog timer restarts. The
sequence to restart consists of the following steps:
1. Write $55 to SWSR.
2. Write $AA to SWSR.
BMT[1:0]
00
01
10
11
Table 5-4 Bus Monitor Period
SYSTEM INTEGRATION MODULE
Bus Monitor Time-Out Period
64 system clocks
32 system clocks
16 system clocks
8 system clocks
MOTOROLA
5-15

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