MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 81

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.2.3 Show Internal Cycles
5.2.4 Register Access
5.2.5 Freeze Operation
MC68336/376
USER’S MANUAL
Because the SIM routes external interrupt requests to the CPU32, the SIM IARB field
value is used for arbitration between internal and external interrupts of the same pri-
ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all
other modules is %0000, which prevents SIM interrupts from being discarded during
initialization. Refer to 5.8 Interrupts for a discussion of interrupt arbitration.
A show cycle allows internal bus transfers to be monitored externally. The SHEN field
in SIMCR determines what the external bus interface does during internal transfer op-
erations. Table 5-1 shows whether data is driven externally, and whether external bus
arbitration can occur. Refer to 5.6.6.1 Show Cycles for more information.
The CPU32 can operate at one of two privilege levels. Supervisor level is more privi-
leged than user level — all instructions and system resources are available at super-
visor level, but access is restricted at user level. Effective use of privilege level can
protect system resources from uncontrolled access. The state of the S bit in the CPU
status register determines access level, and whether the user or supervisor stack
pointer is used for stacking operations. The SUPV bit places SIM global registers in
either supervisor or user data space. When SUPV = 0, registers with controlled access
are accessible from either the user or supervisor privilege level; when SUPV = 1, reg-
isters with controlled access are restricted to supervisor access only.
The FREEZE signal halts MCU operations during debugging. FREEZE is asserted in-
ternally by the CPU32 if a breakpoint occurs while background mode is enabled. When
FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt
timer are affected. The halt monitor and spurious interrupt monitor continue to operate
normally. Setting the freeze bus monitor (FRZBM) bit in SIMCR disables the bus mon-
itor when FREEZE is asserted. Setting the freeze software watchdog (FRZSW) bit dis-
ables the software watchdog and the periodic interrupt timer when FREEZE is
asserted.
SHEN[1:0]
00
01
10
11
Table 5-1 Show Cycle Enable Bits
SYSTEM INTEGRATION MODULE
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
Action
MOTOROLA
5-3