MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 131

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.8.4 Interrupt Processing Summary
MC68336/376
USER’S MANUAL
When arbitration is complete, the module with both the highest asserted interrupt level
and the highest arbitration priority must terminate the bus cycle. Internal modules
place an interrupt vector number on the data bus and generate appropriate internal
cycle termination signals. In the case of an external interrupt request, after the interrupt
acknowledge cycle is transferred to the external bus, the appropriate external device
must respond with a vector number, then generate data and size acknowledge
(DSACK) termination signals, or it must assert the autovector (AVEC) request signal.
If the device does not respond in time, the SIM bus monitor, if enabled, asserts the bus
error signal (BERR), and a spurious interrupt exception is taken.
Chip-select logic can also be used to generate internal AVEC or DSACK signals in re-
sponse to interrupt requests from external devices. Refer to 5.9.3 Using Chip-Select
Signals for Interrupt Acknowledge for more information. Chip-select address match
logic functions only after the EBI transfers an interrupt acknowledge cycle to the exter-
nal bus following IARB contention. If an internal module makes an interrupt request of
a certain priority, and the appropriate chip-select registers are programmed to gener-
ate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that
priority level, chip-select logic does not respond to the interrupt acknowledge cycle,
and the internal module supplies a vector number and generates internal cycle termi-
nation signals.
For periodic timer interrupts, the PIRQ[2:0] field in the periodic interrupt control register
(PICR) determines PIT priority level. A PIRQ[2:0] value of %000 means that PIT inter-
rupts are inactive. By hardware convention, when the CPU32 receives simultaneous
interrupt requests of the same level from more than one SIM source (including external
devices), the periodic interrupt timer is given the highest priority, followed by the IRQ
pins.
A summary of the entire interrupt processing sequence follows. When the sequence
begins, a valid interrupt service request has been detected and is pending.
A. The CPU32 finishes higher priority exception processing or reaches an instruc-
B. The processor state is stacked. The S bit in the status register is set, establish-
C. The interrupt acknowledge cycle begins:
D. Modules that have requested interrupt service decode the priority value on
tion boundary.
ing supervisor access level, and bits T1 and T0 are cleared, disabling tracing.
1. FC[2:0] are driven to %111 (CPU space) encoding.
2. The address bus is driven as follows: ADDR[23:20] = %1111;
3. The request level is latched from the address bus into the IP mask field in
ADDR[3:1]. If request priority is the same as acknowledged priority, arbitration
by IARB contention takes place.
ADDR[19:16] = %1111, which indicates that the cycle is an interrupt
acknowledge CPU space cycle; ADDR[15:4] = %111111111111;
ADDR[3:1] = the priority of the interrupt request being acknowledged; and
ADDR0 = %1.
the status register.
SYSTEM INTEGRATION MODULE
MOTOROLA
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