MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 372

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

D.6.17 Transmit Data RAM
TR[0:F] — Transmit Data RAM
D.6.18 Command RAM
CR[0:F] — Command RAM
CONT — Continue
BITSE — Bits per Transfer Enable
DT — Delay after Transfer
D-54
MOTOROLA
Data that is to be transmitted by the QSPI is stored in this segment. The CPU32
normally writes one word of data into this segment for each queue command to be
executed. Information to be transmitted must be written to transmit data RAM in a
right-justified format. The QSPI cannot modify information in the transmit data RAM.
The QSPI copies the information to its data serializer for transmission. Information re-
mains in transmit RAM until overwritten.
Command RAM is used by the QSPI when in master mode. The CPU32 writes one
byte of control information to this segment for each QSPI command to be executed.
The QSPI cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The periph-
eral chip-select field enables peripherals for transfer. The command control field pro-
vides transfer options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from
the address in NEWQP through the address in ENDQP (both of these fields are in
SPCR2).
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete.
0 = Eight bits
1 = Number of bits set in BITS field of SPCR0.
0 = Delay after transfer is 17
1 = SPCR1 DTL[7:0] specifies delay after transfer PCS valid to SCK.
NOTES:
CONT
CONT
1. The PCS0 bit represents the dual-function PCS0/SS.
—
7
COMMAND CONTROL
BITSE
BITSE
—
6
DT
DT
—
5
REGISTER SUMMARY
f
DSCK
DSCK
sys
—
4
.
PCS3
PCS3
—
3
PERIPHERAL CHIP SELECT
PCS2
PCS2
—
2
PCS1
PCS1
—
1
$YFFD20 – $YFFD3F
$YFFD40 – $YFFD4F
PCS0
PCS0
—
0
USER’S MANUAL
1
1
MC68336/376