MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 369

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

DTL[7:0] — Length of Delay after Transfer
D.6.13 QSPI Control Register 2
SPCR2 — QSPI Control Register 2
SPIFIE — SPI Finished Interrupt Enable
WREN — Wrap Enable
WRTO — Wrap To
Bit 12 — Not Implemented
MC68336/376
USER’S MANUAL
RESET:
SPIFIE
15
0
When the DT bit is set in a command RAM byte, this field determines the length of the
delay after a serial transfer. The following equation is used to calculate the delay:
where DTL equals is in the range of 1 to 255.
A zero value for DTL[7:0] causes a delay-after-transfer value of 8192
If DT is zero in a command RAM byte, a standard delay is inserted.
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion.
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt
enable bit. The CPU32 has read/write access to SPCR2, but the QSM has read
access only. SPCR2 is buffered. New SPCR2 values become effective only after
completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes
execution to restart at the designated location. Reads of SPCR2 return the value of
the register, not the buffer.
0 = QSPI interrupts disabled.
1 = QSPI interrupts enabled.
0 = Wraparound mode disabled.
1 = Wraparound mode enabled.
0 = Wrap to pointer address $0.
1 = Wrap to address in NEWQP.
WREN
14
0
WRTO
13
0
12
0
0
11
0
Delay after Transfer
Standard Delay after Transfer
10
ENDQP[3:0]
0
REGISTER SUMMARY
9
0
8
0
7
0
0
=
----------------------------------- -
System Clock
32 DTL[7:0]
6
0
0
5
0
0
=
------- -
f
17
sys
4
0
0
3
0
NEWQP[3:0]
2
0
f
sys
$YFFC1C
MOTOROLA
.
1
0
D-51
0
0