MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 76

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4-24
MOTOROLA
MICROSEQUENCER
The serial interface uses a full-duplex synchronous protocol similar to the serial pe-
ripheral interface (SPI) protocol. The development system serves as the master of the
serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from
the CPU32 system clock, development system serial logic is unhindered by the oper-
ating frequency of the target processor. Operable frequency range of the serial clock
is from DC to one-half the processor system clock frequency.
The serial interface operates in full-duplex mode — data is transmitted and received
simultaneously by both master and slave devices. In general, data transitions occur on
the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data
is transmitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide, including 16 data bits and a status/control bit (refer
to Figure 4-11). Bit 16 indicates the status of CPU-generated messages. Table 4-7
shows the CPU-generated message types.
CPU
SYNCHRONIZE
EXECUTION
STATUS
UNIT
Figure 4-10 Debug Serial I/O Block Diagram
PARALLEL OUT
RCV DATA LATCH
REGISTER BUS
PARALLEL IN
INSTRUCTION
SERIAL OUT
SERIAL IN
CENTRAL PROCESSOR UNIT
16
16
CONTROL
LOGIC
M
DSCLK
DSO
DSI
DEVELOPMENT SYSTEM
STATUS
0
COMMAND LATCH
PARALLEL OUT
RESULT LATCH
CONTROL
PARALLEL IN
SERIAL OUT
LOGIC
SERIAL IN
DATA
DATA
16
16
USER’S MANUAL
MC68336/376
SERIAL
32 DEBUG I/O BLOCK
CLOCK