MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 387

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

IL[2:0] — Interrupt Level Field
IARB3 — Interrupt Arbitration Bit 3
PIN — Output Pin Status
LOAD — Period and Pulse Width Register Load Control
POL — Output Pin Polarity Control
MC68336/376
USER’S MANUAL
When the interrupt level set specified by IL[2:0] is non-zero, an interrupt request is
generated when the FLAG bit is set.
When the PWMSM generates an interrupt request, IL[2:0] determines which of the
interrupt request signals is asserted. When a request is acknowledged, the CTM4
compares IL[2:0] to a mask value supplied by the CPU32 to determine whether to
respond. IL[2:0] must have a value in the range of $0 (interrupts disabled) to $7
(highest priority).
This bit and the IARB[2:0] field in BIUMCR are concatenated to determine the interrupt
arbitration number for the submodule requesting interrupt service. Refer to D.7.1 BIU
Module Configuration Register for more information on IARB[2:0].
This status bit indicates the logic state present on the PWM output pin.
PIN is a read-only bit; writing to it has no effect.
Setting LOAD reinitializes the PWMSM and starts a new PWM period without causing
a glitch on the output signal.
This bit is always read as a zero. Writing a one to this bit results in the following imme-
diate actions:
This control bit sets the polarity of the PWM output signal. It works in conjunction with
the EN bit and controls whether the PWMSM drives the output pin with the non-
inverted or inverted state of the output flip-flop. Refer to Table D-49.
0 = Logic zero present on the PWM output pin.
1 = Logic one present on the PWM output pin.
0 = No action
1 = Load period and pulse width registers
• The contents of PWMA1 (period value) are transferred to PWMA2.
• The contents of PWMB1 (pulse width value) are transferred to PWMB2.
• The counter register (PWMC) is initialized to $0001.
• The control logic and state sequencer are reset.
• The FLAG bit is set.
• The output flip-flop is set if the new value in PWMB2 is not $0000.
Writing a one to the LOAD bit when the EN bit = 0, (when the
PWMSM is disabled), has no effect.
REGISTER SUMMARY
NOTE
MOTOROLA
D-69