MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 157

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.3.1.2 Status Register
9.3.2 QSPI RAM
9.3.2.1 Receive RAM
9.3.2.2 Transmit RAM
MC68336/376
USER’S MANUAL
tion to restart at the designated location. Reads of SPCR2 return the current value of
the register, not of the buffer. Writing the same value into any control register except
SPCR2 while the QSPI is enabled has no effect on QSPI operation.
SPSR contains information concerning the current serial transmission. Only the QSPI
can set the bits in this register. The CPU32 reads SPSR to obtain QSPI status infor-
mation and writes SPSR to clear status flags.
The QSPI contains an 80-byte block of dual-port access static RAM that can be ac-
cessed by both the QSPI and the CPU32. The RAM is divided into three segments:
receive data RAM, transmit data RAM, and command data RAM. Receive data is in-
formation received from a serial device external to the MCU. Transmit data is informa-
tion stored for transmission to an external device. Command control data defines
transfer parameters. Refer to Figure 9-3, which shows RAM organization.
Data received by the QSPI is stored in this segment. The CPU32 reads this segment
to retrieve data from the QSPI. Data stored in the receive RAM is right-justified. Un-
used bits in a receive queue entry are set to zero by the QSPI upon completion of the
individual queue entry. The CPU32 can access the data using byte, word, or long-word
addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The
CPU32 uses this information to determine which locations in receive RAM contain val-
id data before reading them.
Data that is to be transmitted by the QSPI is stored in this segment and must be written
to transmit RAM in a right-justified format. The QSPI cannot modify information in the
transmit RAM. The QSPI copies the information to its data serializer for transmission.
Information remains in transmit RAM until overwritten.
51E
500
RECEIVE
WORD
RAM
RRD
RRE
RR0
RR1
RR2
RRF
QUEUED SERIAL MODULE
Figure 9-3 QSPI RAM
53E
520
TRANSMIT
WORD
RAM
TRD
TRE
TRF
TR0
TR1
TR2
540
54F
COMMAND
BYTE
RAM
CRD
CRE
CR0
CR1
CR2
CRF
MOTOROLA
QSPI RAM MAP
9-7