MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 118

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.7 Reset
5.7.1 Reset Exception Processing
5.7.2 Reset Control Logic
5-40
MOTOROLA
SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion
of the data bus is valid during the cycle. During a byte write to an internal address, the
portion of the bus that represents the byte that is not written reflects internal bus con-
ditions, and is indeterminate. During a byte write to an external address, the data mul-
tiplexer in the SIM causes the value of the byte that is written to be driven out on both
bytes of the data bus.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM.
The RESET input is synchronized to the system clock. If there is no clock when
RESET is asserted, reset does not occur until the clock starts. Resets are clocked to
allow completion of write cycles in progress at the time RESET is asserted.
Reset procedures handle system initialization and recovery from catastrophic failure.
The MCU performs resets with a combination of hardware and software. The SIM
determines whether a reset is valid, asserts control signals, performs basic system
configuration and boot ROM selection based on hardware mode-select inputs, then
passes control to the CPU32.
The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing, and can be caused by internal or external
events. Exception processing makes the transition from normal instruction execution
to execution of a routine that deals with an exception. Each exception has an assigned
vector that points to an associated handler routine. These vectors are stored in the
exception vector table. The exception vector table consists of 256 four-byte vectors
and occupies 1024 bytes of address space. The exception vector table can be relocat-
ed in memory by changing its base address in the vector base register (VBR). The
CPU32 uses vector numbers to calculate displacement into the table. Refer to 4.9 Ex-
ception Processing for more information.
Reset is the highest-priority CPU32 exception. Unlike all other exceptions, a reset oc-
curs at the end of a bus cycle, and not at an instruction boundary. Handling resets in
this way prevents write cycles in progress at the time the reset signal is asserted from
being corrupted. However, any processing in progress is aborted by the reset excep-
tion and cannot be restarted. Only essential reset tasks are performed during excep-
tion processing. Other initialization tasks must be accomplished by the exception
handler routine. Refer to 5.7.9 Reset Processing Summary for details on exception
processing.
SIM reset control logic determines the cause of a reset, synchronizes reset assertion
if necessary to the completion of the current bus cycle, and asserts the appropriate re-
set lines. Reset control logic can drive four different internal signals:
SYSTEM INTEGRATION MODULE
USER’S MANUAL
MC68336/376