MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 209

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.12.5 Periodic/Interval Timer
MC68336/376
USER’S MANUAL
The MCU system clock frequency is the basis of QADC timing. The QADC requires
that the system clock frequency be at least twice the QCLK frequency. Refer to Table
A-13 for information on the minimum and maximum allowable QCLK frequencies.
Example 1 in Figure 8-9 shows that when PSH = 3, the QCLK remains high for four
system clock cycles. It also shows that when PSL = 3, the QCLK remains low for four
system clock cycles.
In order to tune QCLK for the fastest possible conversion time for any given system
clock frequency, the QADC permits one more programmable control of the QCLK high
and low time. The PSA bit in QACR0 allows the QCLK high phase to be stretched for
a half cycle of the system clock, and correspondingly, the QCLK low phase is short-
ened by a half cycle of the system clock.
Example 2 in Figure 8-9 is the same as Example 1, except that the PSA bit is set. The
QCLK high phase has 4.5 system clock cycles; the QCLK low phase has 3.5 system
clock cycles.
The QADC periodic/interval timer can be used to generate trigger events at program-
mable intervals to initiate scans of queue 2. The periodic/interval timer is held in reset
under the following conditions:
Two other conditions which cause a pulsed reset of the timer are:
During the low-power stop mode, the periodic/interval timer is held in reset. Since low-
power stop mode initializes QACR2 to zero, a valid periodic or interval timer mode
must be written to QACR2 when exiting low-power stop mode to release the timer from
reset.
Example
Number
• Queue 2 is programmed to any queue operating mode which does not use the
• Interval timer single-scan mode is selected, but the single-scan enable bit is
• IMB system reset or the master reset is asserted
• The QADC is placed in low-power stop mode with the STOP bit
• The IMB FREEZE line is asserted and the QADC FRZ bit is set to one
• Rollover of the timer counter
• A queue operating mode change from one periodic/interval timer mode to another
periodic/interval timer mode
cleared to zero
periodic/interval timer
1
2
Control Register 0 Information
PSH[4:0]
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
7
7
Table 8-4 QADC Clock Programmability
PSA
0
1
PSL[2:0]
7
7
QCLK (MHz)
Input Sample Time (IST) = %00
1.0
1.0
f
sys
Conversion Time ( s)
= 20.97
18.0
18.0
MOTOROLA
8-27