IP-CPRI Altera, IP-CPRI Datasheet - Page 102

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–6
Table 6–12. CPRI_HW_RESET—Hardware Reset From Control Word—Offset: 0x20 (Part 2 of 2)
Table 6–13. CPRI_PHY_LOOP—Physical Layer Loopback Control—Offset: 0x24 (Part 1 of 2)
CPRI MegaCore Function User Guide
reset_hw_en
reset_out_en
reset_gen_force
reset_gen_en
Note to
(1) This register field is a read-to-clear field. You must read the register twice to read the true value of the field after frame synchronization is
RSRV
loop_resync
RSRV
achieved. If you observe this bit asserted during link initialization, read the register again after link initialization to confirm any errors.
Table
Field
Field
6–12:
For additional information about the CPRI_HW_RESET register, refer to
Function Reset Process” on page
[31:5]
[4]
[3:1]
Bits
[3]
[2]
[1]
[0]
Bits
UR0
RC
UR0
Access
RW
RW
RW
RW
Access
(1)
Reserved.
Indicates that reset resynchronization is detected. This bit is
typically set when the CPRI receiver clock and cpri_clkout
have different frequencies, as measured in the physical layer
internal loopback path.
Reserved.
Enable generation of reset request or acknowledge by CPRI
transmitter, as indicated by the hw_reset_assert input signal.
This enable bit has higher priority than the reset_gen_en bit; if
this enable bit is set, the reset_gen_force bit is ignored.
Note that when a CPRI RE slave detects a reset request in
incoming CPRI communication, and the reset_hw_en bit is
set, the user must assert the hw_reset_assert input signal to
the CPRI RE slave, to force it to send a reset acknowledge by
setting the reset bit in outgoing CPRI communication at
Z.130.0.
Enable reset output.
Force generation of reset request or acknowledge by CPRI
transmitter.
Enable generation of reset request or acknowledge by CPRI
transmitter, as indicated by the reset_gen_force bit. This
enable bit has lower priority than the reset_hw_en bit; if the
reset_hw_en bit is set, this bit and the reset_gen_force bit
are ignored.
4–13.
Function
Function
December 2010 Altera Corporation
Chapter 6: Software Interface
CPRI Interface Registers
“MegaCore
27'h0
1’h0
2'h0
Default
1'h0
1'h0
1'h0
1'h0
Default