IP-CPRI Altera, IP-CPRI Datasheet - Page 69

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Delay Measurement
December 2010 Altera Corporation
Rx Path Delay to AUX Output: Calculation Example
This section shows you how to calculate the Rx path delay to the AUX output, based
on the example shown in
page
MegaCore function that runs at CPRI data rate 3072 Mbps and targets an Arria II GX
device.
To calculate the Rx path delay, follow these steps:
1. Consult
2. Calculate the latency through the Rx Receive buffer, including phase alignment, by
3. Read the value in the rx_byte_delay field of the CPRI_RX_DELAY register — when
4. Consult
5. Calculate the full Rx path delay to the AUX interface by adding the values you
Rx Path Delay to AxC Output
The delay through the MAP interface depends on whether the AxC data
communication is programmed in FIFO mode or in synchronous buffer mode. In
FIFO mode, the delay through the mapN Rx buffer depends on your programmed
threshold value and the application. The data is not sent to the data channel untiI the
buffer threshold is reached, so the wait time in the buffer depends on data received on
the CPRI link before and after the current data. In synchronous buffer mode, because
programmed offsets control the mapN Rx buffer pointers, the delay can be quantified.
family. For the example, the table yields T_txv_RX = 4.65 cpri_clkout clock cycles.
following the steps in
page 4–43
calculations shown in
delay through the Rx Receive buffer of 33.236 cpri_clkout clock cycles.
the value in rx_byte_delay is non-zero, a byte alignment delay of one
cpri_clkout cycle occurs in the Rx path. When the value is zero, no byte
alignment delay occurs.
MegaCore function to the AUX interface. For the example, the duration of this
delay is five cpri_clkout clock cycles.
derived in step
delay as follows:
Rx path delay = T_txv_RX + <delay through Rx Receive buffer>
The best case Rx path delay has zero byte alignment delay, for a total delay of
42.886 cpri_clkout clock cycles.
4–43. This example walks through the calculation for the case of a CPRI
Table 4–6 on page 4–42
Table 4–8 on page 4–44
for your CPRI MegaCore function instance. For the example, the
= 4.65 + 33.236 + 1 + 5 cpri_clkout clock cycles
= 43.886 cpri_clkout clock cycles
1
through step 4. For the example, calculate the worst case Rx path
“CPRI Receive Buffer Delay Calculation Example” on
“CPRI Receive Buffer Delay Calculation Example” on
“CPRI Receive Buffer Delay Calculation Example”
+ <worst case variable byte alignment delay>
+ <delay to AUX IF>
for the correct value of T_txv_RX for your device
to determine the delay through the CPRI
CPRI MegaCore Function User Guide
yield a
4–45