IP-CPRI Altera, IP-CPRI Datasheet - Page 130

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

7–6
Running the Testbenches
CPRI MegaCore Function User Guide
The auto-rate negotiation testbench performs auto-rate negotiation. Refer to
Appendix B, Implementing CPRI Link Auto-Rate Negotiation
To run the CPRI MegaCore function testbenches, perform the following steps:
1. In the Quartus II software, create a Quartus II project using the New Project
2. Generate the CPRI MegaCore function DUT instance with the properties shown in
Table 7–4. MegaWizard Plug-in Manager Options for CPRI MegaCore Function DUT
Parameter
Device family
Language
File name
Line rate
Operation mode
Number of antenna-carrier interfaces
Enable auto-rate negotiation
Include MAC block
Notes to
(1) If you use a different path or file name, you must edit the compile_<variation>.do file to refer to the correct file
(2) Altera does not support an example testbench for an RE slave DUT. An RE slave in loopback configuration cannot
Wizard available from the File menu. The project targets the same device as your
intended DUT. Refer to
Table
for the DUT.
achieve frame synchronization, because the receive CPRI interface must lock onto the K28.5 character before the
transmit CPRI interface can begin sending K28.5 characters. Therefore, no K28.5 character is ever transmitted on
the RE slave loopback CPRI link. To simulate an RE slave, you must connect the RE slave DUT to an RE master or
REC CPRI MegaCore function.
Table
7–4.
(1)
7–4:
Table
7–4.
Value
tb_altera_cpri_autorate: Stratix IV GX
tb_altera_cpri_c4gx_autorate: Cyclone IV GX
All other testbenches: Any
VHDL
<working directory>\cpri_top_level
0.6144 Gbps
Master
tb_altera_cpri and tb_altera_cpri_mii: 3
tb_altera_cpri_mii_noiq, tb_altera_cpri_autorate, and
tb_altera_cpri_c4gx_autorate: 0
tb_altera_cpri_autorate and
tb_altera_cpri_c4gx_autorate: On
All other testbenches: Off
tb_altera_cpri and tb_altera_cpri_c4gx_autorate: On
All other testbenches: Off
(2)
December 2010 Altera Corporation
for details.
Chapter 7: Testbenches
Running the Testbenches