IP-CPRI Altera, IP-CPRI Datasheet - Page 118

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–22
Table 6–57. ETH_TX_DATA—Ethernet Tx Data—Offset: 0x220
Table 6–58. ETH_TX_DATA_WAIT—Ethernet Tx Data with Wait-State Insertion—Offset: 0x224
Table 6–59. ETH_ADDR_MSB—Ethernet MAC Address MSB—Offset: 0x22C
Table 6–60. ETH_ADDR_LSB—Ethernet MAC Address LSB—Offset: 0x230
Table 6–61. ETH_HASH_TABLE—Ethernet Multicast Filtering Hash Table—Offset: 0x234
Table 6–62. ETH_FWD_CONFIG—Ethernet Forwarding Configuration—Offset: 0x244
CPRI MegaCore Function User Guide
tx_data
tx_data
RSRV
mac[47:32]
mac[31:0]
hash
RSRV
tx_start_thr
tx_st_fwd
Field
Field
Field
Field
Field
Field
[31:17] UR0
[16:1]
[0]
[31:0] RW
[31:0] RW
Bits
Bits
Bits
RW
RW
Access
Access
Access
[31:16] UR0
[15:0]
[31:0]
[31:0]
Bits
Bits
Bits
RW
RW
RW
Ethernet Tx frame data. If the Ethernet transmitter module writes
Ethernet data to this register, if data is not ready when the module
expects it, the Ethernet transmitter module aborts the packet.
Ethernet Tx frame data. If the Ethernet transmitter module writes
Ethernet data to this register, it waits until data is ready, unless the
CPU times out the operation.
Access
Access
Access
Reserved.
Transmit start threshold. If store-and-forward mode is disabled,
transmission to the CPRI link starts when this number of 32-bit
words are stored in the Tx buffer.
Transmit store-and-forward mode. In store-and-forward mode, a
full packet is stored in the Tx buffer before transmission starts.
Packets longer than the Tx buffer are aborted.
Reserved.
Most significant bits (16 bits) of local Ethernet MAC
address.
Least significant bits (32 bits) of local Ethernet MAC
address.
32-bit hash table for multicast filtering. If the group
address bit of the destination MAC address is set, and
multicast address filtering is enabled, this register
filters the packets to be accepted and discarded, as
follows:
If every bit set in this register is also set in the lower 32
bits of the destination MAC address, the packet is
accepted. Otherwise, the packet is discarded.
Function
Function
Function
Function
Function
Function
December 2010 Altera Corporation
Chapter 6: Software Interface
Ethernet Registers
16'h0
16'h0
32'h0
32'h0
15’h0
16’h0004
1'h0
Default
Default
Default
Default
1'h0
1'h0
Default
Default