IP-CPRI Altera, IP-CPRI Datasheet - Page 71

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Delay Measurement
December 2010 Altera Corporation
T14, Toffset, Round-Trip Delay, and Round-Trip Cable Delay Calculations
The delay through the mapN Tx buffer depends on whether the AxC data
communication is programmed in FIFO mode or in synchronous buffer mode. In
FIFO mode, the delay through the mapN Tx buffer depends on your threshold value
and the application. Depending on the size of the data burst, the Tx buffer may not
reach the threshold until the next data burst arrives on the data channel. In
synchronous buffer mode, because programmed offsets control the mapN Tx buffer
pointers, the delay can be quantified.
The Tx path delay to output from the MAP interface block has the same components
and
delay from the MAP interface block to output on the CPRI transmitter interface. In
synchronous buffer mode, the delay from the individual AxC interfaces to output
from the MAP interface block is the time the data spends in the mapN Tx buffer. This
delay is one cycle if the sample rate is a multiple of 3.84 MHz, and two cycles
otherwise. Refer to
The round-trip cable delay is the delay from the REC end of the CPRI downlink to the
REC end of the CPRI uplink. This round-trip cable delay is shown as T14 in
Figure 4–19 on page
we ensure an accuracy of ±16.276 ns in the measurement of the round-trip cable delay
in a single-hop configuration.
In contrast, the rx_round_trip_delay field of the CPRI_ROUND_DELAY register records
the total round-trip delay from the start of the internal transmit radio frame in the
REC to the start of the internal receive radio frame in the REC, that is, from SAP to
SAP. The register value is only available in CPRI REC or RE masters.
You must subtract the internal delays through the RE or REC master from this register
value to determine the value of T14, the round-trip cable delay, for the current hop.
CPRI V4.1 Specification requirements R-20 and R-21 address the round-trip delay.
Requirement R-20 addresses the measurement without including the cable delay, and
requirement R-21 includes the cable delay. Both requirements state that the variation
must be no more than ±16.276 ns.
Because the CPRI REC master and the CPRI RE slave might be on different devices,
the following formulas specify the source MegaCore function (REC or RE) for the
delays in each calculation.
Round-Trip and Cable Delay Calculations for a Single-Hop Configuration
The rx_round_trip_delay field of the CPRI_ROUND_DELAY register records the delay
between the outgoing cpri_tx_rfp signal and the outgoing cpri_rx_rfp signal. The
cpri_tx_rfp signal is bit [0] of the aux_tx_status_data output signal bus, asserted in
response to the assertion of the incoming signal cpri_tx_sync_rfp, which is bit [64] of
the aux_tx_mask_data input signal, or in response to the 10 ms radio frame start based
on the internal frame count in the CPRI transmitter interface. The cpri_rx_rfp signal
is bit [75] of the aux_rx_status_data output signal bus, asserted in response to the
start of the 10 ms radio frame on the CPRI receiver interface. In a single-hop system,
shown in
components:
■
T12—The delay from CPRI REC to CPRI RE
2
as the Tx path delay from the AUX interface. These components comprise the
Figure 4–19 on page
“CPRI MAP Transmitter Interface” on page
4–40. The CPRI V4.1 Specification requirement R-21 requires that
4–40, the round-trip cable delay T14 has the following
CPRI MegaCore Function User Guide
4–31.
4–47
1