IP-CPRI Altera, IP-CPRI Datasheet - Page 19

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Specify Constraints
Specify Constraints
December 2010 Altera Corporation
Simulate the Design
f
1
f
■
During the design process, to check your design quickly, you can simulate your CPRI
MegaCore function variation using the IP functional simulation model and the VHDL
demonstration testbench. The IP functional simulation model and testbench files are
generated in your project directory. The directory also includes scripts to compile and
run the demonstration testbench. The testbench demonstrates how to instantiate a
model in a design and includes simple stimuli to control the user interfaces of the
CPRI MegaCore function.
A Verilog HDL testbench is not generated. If you specify Verilog HDL in the
MegaWizard Plug-in Manager, it generates a Verilog HDL IP functional simulation
model for the CPRI MegaCore function. You can use this model with the VHDL
demonstration testbench for simulation using a mixed-language simulator.
Altera provides a Synopsys Design Constraints (.sdc) file that you must apply to
ensure that the CPRI MegaCore function meets design timing requirements. In most
cases the script requires modification for your design.
For information about timing analyzers, refer to the Quartus II Help and the
Analysis
Quartus II software
MegaWizard Plug-in Manager
A complete list of models or libraries required
to simulate the CPRI MegaCore function
IP functional simulation models
After you generate the system, Altera recommends that you create assignments for
the high-speed transceiver VCCH settings by performing the following steps:
a. In the Quartus II window, on the Assignments menu, click Assignment Editor.
b. In the <<new>> cell in the To column, type the top-level signal name for your
c. Double-click in the Assignment Name column and click I/O Standard.
d. Double-click in the Value column and click your standard (for example, 1.5-V
e. In the new <<new>> row, repeat steps
CPRI MegaCore function instance gxb_txdataout signal.
PCML).
instance gxb_rxdatain signal.
section in volume 3 of the Quartus II Handbook.
For Information About
See the Quartus II Help topics:
“About the Quartus II Software”
“About the MegaWizard Plug-In Manager”
compile[_<variation>]_<HDL>.do scripts provided
with the demonstration testbenches described in
Chapter 7, Testbenches
Simulating Altera Designs
the Quartus II Handbook
b
to
d
for your CPRI MegaCore function
CPRI MegaCore Function User Guide
Refer To
chapter in volume 3 of
Timing
2–3