IP-CPRI Altera, IP-CPRI Datasheet - Page 31

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Clocking and Reset Structure
Figure 4–2. CPRI MegaCore Function Slave Clocking in Arria II GX and Cyclone IV GX Devices
Note to
(1) The clk_ex_delay input clock can be driven by a cleanup PLL. However, it can also be driven by other clock logic that provides the correct M/N
December 2010 Altera Corporation
gxb_txdataout
gxb_rxdatain
ratio for the accuracy required by the application. Refer to
Figure
gxb_refclk
4–2:
rx_cruclk
ALTGX
Figure 4–2
RE slave with CPRI line rate greater than 0.6144 Gbps in an Arria II GX or
Cyclone IV GX device.
CDR
pll_clkout
rx_clkout
tx_clkout
pll_inclk
Clean-Up PLL
shows the clock diagram for a CPRI MegaCore function configured as an
data
gxb_pll_inclk
16
16
data
“Extended Rx Delay Measurement” on page
Divide
Divide
by 2
by 2
FIFO
FIFO
32
clk_ex_delay
cpri_clkout
data
32
Sync Buffer
CPRI RX
Rx Elastic
CPRI TX
(1)
clk
clk
32
cpri_tx_aux_data
32
cpri_rx_aux_data
32
32
Ethernet MAC
data
HDLC
4–42.
clk
clk
data
CPRI MegaCore Function
CPRI MegaCore Function User Guide
CPRI Tx
Interface
CPRI Rx
Interface
FIFO
FIFO
MAP
MAP
clk
MII Interface
Interface
CPU
mapXX_tx_data
mapXX_tx_clk
mapXX_rx_clk
mapXX_rx_data
cpri_mii_txclk
cpri_mii_rxclk
cpu_clk
cpu_writedata
cpu_readdata
4–7