IP-CPRI Altera, IP-CPRI Datasheet - Page 54

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–30
Figure 4–14. User-Controlled Delays to the AxC Data Channels
CPRI MegaCore Function User Guide
cpri_rx_rfp / _hfp
Write to mapN Rx buffer according to CPRI_MAP_RX_OFFSET value:
mapN_rx_resync
Read from mapN Rx buffer in the first read cycle after the resync signal:
cpri_rx_start
Asserting the resynchronization signal ensures correct alignment between the RF
implementation and the CPRI basic frame at the appropriate offset from the start of
the 10 ms radio frame. In addition to ensuring that application-specific constraints are
accommodated, the system can set the CPRI_START_OFFSET_RX register to an offset that
lags the desired frame position in the CPRI transmission, in anticipation of the delays
from the CPRI Rx interface and through the antenna-carrier interface Rx buffer. For
information about these delays, refer to
Figure 4–15
registers in ensuring correct alignment.
The values programmed in the CPRI_START_OFFSET_RX register control the assertion of
the cpri_rx_start signal. The values in the start_rx_offset_z, start_rx_offset_x,
and start_rx_offset_seq fields specify a hyperframe number, basic frame number,
and word number in the basic frame, respectively, within the 10 ms frame. The system
source of the AxC payload transmits the AxC container block on the CPRI link at a
specific location in the 10 ms frame; the system programs the information for this
location in the CPRI_START_OFFSET_RX register. The CPRI slave receiver learns the
location of the AxC container block from the CPRI_START_OFFSET_RX register. For
example, if the CPRI_START_OFFSET_RX register is programmed with the value
0x00020001, the CPRI receiver asserts the cpri_rx_start signal at word index 2 of
basic frame 1 of hyperframe 0 in the 10ms frame. The data channel application
samples the cpri_rx_start signal, detects it is asserted, and then optionally asserts
the mapN_rx_resync signal to indicate that the AxC container block can be written to
the Rx MAP buffer for this data channel. Assertion of the mapN_rx_resync signal
resets the read pointer of current antenna-carrier interface (mapN) Rx buffer to zero,
so that all the data in the buffer is transmitted to the data channel. The mapN_rx_data
can safely be sampled by the data channel one cycle after the mapN_rx_resync signal is
asserted.
On the CPRI side of the mapN Rx buffer, the CPRI MAP receiver interface transfers
data to the mapN Rx buffer. The offset programmed in the CPRI_MAP_OFFSET_RX
register tells the CPRI MAP receiver interface when to reset the write pointer of the
mapN Rx buffer and start transferring data to the buffer from the CPRI receiver
interface. In advanced mapping modes, the K counter is reset to zero at the same time,
so that it advances from zero with the transfer of the data to the MAP Rx buffer,
tracking the packing of the CPRI data contents into the AxC container block.
shows the roles of the CPRI_START_OFFSET_RX and CPRI_MAP_OFFSET_RX
CPRI_MAP_RX_OFFSET
CPRI_START_RX_OFFSET
sample 0 sample 1sample 2 sample 3 sample 4 sample 5 sample 6
sample 0 sample 1sample 2 sample 3 sample 4 sample 5 sample 6
“Rx Path Delay” on page
December 2010 Altera Corporation
Chapter 4: Functional Description
4–40.
CPRI MAP Interface Module