IP-CPRI Altera, IP-CPRI Datasheet - Page 84

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–4
Table 5–6. Transceiver Signals (Part 2 of 2)
CPRI MegaCore Function User Guide
reconfig_write
reconfig_done
gxb_pll_locked
gxb_rx_pll_locked
gxb_rx_freqlocked
gxb_powerdown
gxb_rx_disperr[1:0]
gxb_rx_errdetect[1:0]
Note to
(1) Refer
transceiver channels—whether in two CPRI MegaCore function instances or in a CPRI MegaCore function and in another component—in the
same quad.
Table
to“Instantiate Multiple CPRI MegaCore Functions” on page 2–4
5–6:
Signal
In addition to customization of the transceiver through the transceiver parameter
editor, you can use the transceiver reconfiguration block to dynamically modify the
parameter interface. The dynamic reconfiguration block lets you reconfigure the
following PMA settings:
■
■
■
Pre-emphasis
Equalization
Offset cancellation
Direction
Input
Input
Output
Output
Output
Input
Output
Output
Indicates the user is writing to the dynamic reconfiguration controller to
implement the auto-rate negotiation feature. Asserting this signal instructs
the CPRI reset controller to perform the reset sequence for dynamic
reconfiguration of the transceiver. For details about dynamic
reconfiguration, refer to the relevant device handbook.If you are not using
the auto-rate configuration feature, you must tie this input to 0.
Indicates the dynamic reconfiguration controller has completed the
reconfiguration operation. Asserting this signal instructs the CPRI reset
controller to complete the reset sequence for dynamic reconfiguration of the
transceiver. For details about dynamic reconfiguration, refer to the relevant
device handbook. If you are not using the auto-rate configuration feature,
you must tie this input to 0.
Indicates the transceiver transmitter PLL is locked to the input reference
clock. This signal is asynchronous.
Indicates the transceiver CDR is locked to the input reference clock. This
signal is asynchronous.
Transceiver clock data recovery (CDR) lock mode indicator. If this signal is
high, the transceiver CDR is in lock-to-data (LTD) mode. If this signal is low,
the transceiver CDR is in lock-to-reference clock (LTR) mode.
Transceiver block power down. This signal resets and powers down all
analog and digital circuitry in the transceiver block, including physical
coding sublayer (PCS), physical media attachment (PMA), clock multiplier
unit (CMU) channels, and central control unit (CCU). This signal does not
affect the gxb_refclk buffers and reference clock lines.
All the gxb_powerdown input signals of MegaCore functions intended to be
placed in the same quad must be tied together. The gxb_powerdown signal
must be tied low or must remain asserted for at least 2 ms whenever it is
asserted.
Transceiver 8B/10B disparity error indicator. If either bit is high, a disparity
error was detected on the associated received code group.
Transceiver 8B/10B code group violation or disparity error indicator. If either
bit is high, a code group violation or disparity error was detected on the
associated received code group. Use the gxb_rx_disperr signal to
determine whether this signal indicates a code group violation or a disparity
error. For details, refer to the relevant device handbook.
for information about how to successfully combine multiple high-speed
Description
December 2010 Altera Corporation
Physical Layer Signals
Chapter 5: Signals