IP-CPRI Altera, IP-CPRI Datasheet - Page 56

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–32
Figure 4–15. User-Controlled Delays in Accepting Data From the AxC Data Channels
CPRI MegaCore Function User Guide
mapN_tx_resync
Write to mapN Tx buffer in the first write cycle after the resync signal:
Read from mapN Tx buffer according to CPRI_MAP_TX_OFFSET value:
cpri_tx_sync_rfp
cpri_tx_start
cpri_tx_rfp
Asserting the resynchronization signal ensures correct alignment between the RF
implementation and the CPRI basic frame at the appropriate offset from the start of
the 10 ms radio frame. In addition to ensuring that application-specific constraints are
accommodated, the system can set the CPRI_START_OFFSET_TX register to an offset that
precedes the desired frame position in the CPRI transmission, in anticipation of the
delays through the antenna-carrier interface Tx buffer and out to the CPRI Tx frame
buffer. For information about these delays, refer to
Figure 4–15
registers in ensuring correct alignment.
The values programmed in the CPRI_START_OFFSET_TX register control the assertion of
the cpri_tx_start signal by the CPRI transmitter. The values in the
start_tx_offset_z, start_tx_offset_x, and start_tx_offset_seq fields specify a
hyperframe number, basic frame number, and word (sequence) number in the basic
frame, respectively, within the 10 ms frame.
The system source of the AxC payload transmits the AxC container block on the data
channel to target a specific location in the 10 ms frame; the system programs the
information for this location in the CPRI_START_OFFSET_TX and CPRI_MAP_OFFSET_TX
registers. The CPRI transmitter learns the location of the AxC container block on the
AxC interface from the CPRI_START_OFFSET_TX register. For example, if the
CPRI_START_OFFSET_TX register is programmed with the value 0x000595FE, the CPRI
transmitter must assert the cpri_tx_start signal at word index 5 of basic frame 254 of
hyperframe 149 in the 10ms frame. Altera recommends that the data channel
application sample the cpri_tx_start signal, and when it detects the cpri_tx_start
signal is asserted, assert the mapN_tx_resync signal to indicate that the samples on
mapN_tx_data can begin to fill the data words at the specified position in the CPRI
frame. Assertion of the mapN_tx_resync signal resets the write pointer of the current
antenna-carrier interface (mapN) Tx buffer to zero, so that the entire buffer is
available to receive the data from the data channel. The data on mapN_tx_data[31:0]
can safely be loaded in the mapN Tx buffer one cycle after the mapN_tx_resync signal
is asserted.
CPRI_START_TX_OFFSET
shows the roles of the CPRI_START_OFFSET_TX and CPRI_MAP_OFFSET_TX
CPRI_MAP_TX_OFFSET
sample 0 sample 1sample 2 sample 3 sample 4 sample 5 sample 6
sample 0 sample 1sample 2 sample 3 sample 4 sample 5 sample 6
“Tx Path Delay” on page
December 2010 Altera Corporation
Chapter 4: Functional Description
CPRI MAP Interface Module
4–46.