IP-CPRI Altera, IP-CPRI Datasheet - Page 52

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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CPRI MegaCore Function User Guide
In 16-bit width mode, when map_mode has value 2’b01, all of the data bits in a CPRI
frame pass through the AxC interface to or from the CPRI MegaCore function. When
map_mode has value 2’b10, the initial 32-bit sets of data in the CPRI frame pass through
the AxC interface. However, when map_mode has value 2’b10, the spare bytes—bytes
at the end of the IQ data block that do not fill another complete 32-bit word—are
dropped in the outgoing data channel, and become reserved bits in the CPRI frame
after the data arrives on the incoming data channel; these bits are expected to not
contain valid AxC data in the CPRI frame.
For example, for a CPRI MegaCore function running at CPRI data rate 1228.8 Gbps,
the number of data bits in a CPRI basic frame is 240. (Refer to
If K (specified in the K field of the CPRI_MAP_TBL_CONFIG register) has value two, 480
bits, or 60 bytes, of data are sent or received on the data channel. In 16-bit mode, when
map_mode has value 2’b01, with offsets all set to zero, all of the data bits are packed in
15 timeslots. When map_mode has value 2’b10, 32 of these data bits are dropped, 16
from each CPRI frame, and the remaining data bits require only 14 timeslots. The first
seven timeslots are identical in the two cases. However, in the eighth timeslot, when
map_mode has value 2’b01, the final two bytes of the data from or for the first CPRI
frame are followed by the first two bytes of the second CPRI frame data. The
following timeslot holds the third through sixth byte of the second CPRI frame data,
and so on. The fourteenth timeslot holds the 23rd through the 26th byte of the second
CPRI frame data, and the fifteenth timeslot holds the 27th through the 30th bytes of
the second CPRI frame data. In contrast, when map_mode has value 2’b10, the final two
bytes of the data from or for the first CPRI frame are dropped or assumed reserved.
The eighth timeslot holds the first four bytes of the second CPRI frame data, instead.
Four-byte words of data from or for the second CPRI frame appear in the eighth
through the fourteenth timeslots, and the final two bytes of the second CPRI frame
data are dropped.
Figure 4–13. Example of Difference Between Two AxC Advanced Mapping Modes
map_mode = 2’b01:
Timeslot number: 0
map_mode = 2’b10:
Timeslot number: 0
Figure 4–13
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illustrates this example.
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December 2010 Altera Corporation
Chapter 4: Functional Description
Table 4–4 on page
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CPRI MAP Interface Module
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