IP-CPRI Altera, IP-CPRI Datasheet - Page 73

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Data Link Layer for Fast Control and Management Channel (Ethernet)
Data Link Layer for Fast Control and Management Channel (Ethernet)
December 2010 Altera Corporation
Ethernet Transmitter
In the CPRI MegaCore function, the Ethernet Media Access Control (MAC), or fast
data link layer, passes Ethernet data from the CPU interface to the CPRI transmitter
interface block, and from the CPRI receiver block to the CPU interface. The CPRI
specification dictates that a CPRI hyperframe that contains Ethernet data also contain
a pointer to the start of that data in control byte Z.194.0. The pointer value 0x0
indicates that no Ethernet channel is supported in the current hyperframe. A valid
pointer holds a subchannel index value between 0x24 and 0x3F, inclusive. The Altera
CPRI MegaCore function reserves subchannels 0x10 to 0x23; the start of Ethernet data
can be located in any following word in the hyperframe. The length of the Ethernet
data can extend beyond the end of the hyperframe; if a received Ethernet frame
exceeds 1536 bytes, the Ethernet module resets, unless the rx_long_frame_en bit of
the ETH_CONFIG_1 register is set.
The CPRI transmitter reads the pointer value from the tx_fast_cm_ptr field of the
CPRI_CM_CONFIG register and writes it in CPRI control byte Z.194.0 in the outgoing
CPRI hyperframe. The rx_fast_cm_ptr field of the CPRI_CM_STATUS register holds the
current pointer value, determined during the software set-up sequence or by dynamic
modification, in which the same new pointer value is received in CPRI control byte
Z.194.0 four hyperframes in a row.
Software can configure the Ethernet channel by writing to the ETH_CONFIG_1 register
through the CPRI MegaCore function Avalon-MM CPU interface. For additional
information about this register, refer to
The Ethernet transmitter module receives data on the Ethernet channel and writes it
to an Ethernet Tx buffer, from which the CPRI transmitter module transmits it on the
CPRI link.
Ethernet Data Transfer
The Ethernet transmitter module sends Ethernet data to an Ethernet Tx buffer
through the ETH_TX_DATA or ETH_TX_DATA_WAIT register. Status bits in the
ETH_TX_STATUS register indicate when the Ethernet Tx buffer is ready to receive one
word, and when it is ready to receive a 32-bit packet. Before the Ethernet packet
end-of-packet word is written to the ETH_TX_DATA or ETH_TX_DATA_WAIT register, the
Ethernet transmitter module sets the tx_eop bit and configures the tx_length field in
the ETH_TX_CONTROL register to indicate how many bytes in this word are padding. If
the Ethernet transmitter module writes data to the ETH_TX_DATA register when the
Ethernet Tx buffer is not ready, the tx_abort bit is set in the ETH_TX_STATUS register
and the current Ethernet packet is aborted. The ETH_TX_DATA_WAIT register can accept
data when the Ethernet Tx buffer is not ready for new data.
The Ethernet transmitter module must write frame data to the ETH_TX_DATA register
continuously. The Ethernet transmitter module ensures the correct bit order for
transmission on the CPRI link. If the crc_enable field of the ETH_CONFIG_2 register has
value 0, you must insert the CRC in the frame data, because the Ethernet receiver
module checks CRC. In this case, you must reverse the bit order of the CRC bytes so
that the most significant byte of the CRC is transmitted first.
Chapter 6, Software
CPRI MegaCore Function User Guide
Interface.
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