IP-CPRI Altera, IP-CPRI Datasheet - Page 86

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–6
CPRI MII Interface Signals
Table 5–8. CPRI MII Receiver Interface Signals
Table 5–9. CPRI MII Transmitter Interface Signals (Part 1 of 2)
CPRI MegaCore Function User Guide
cpri_mii_rxclk
cpri_mii_rxwr
cpri_mii_rxdv
cpri_mii_rxer
cpri_mii_rxd[3:0]
cpri_mii_txclk
cpri_mii_txen
cpri_mii_txer
CPRI MII Interface Receiver Signals
CPRI MII Interface Transmitter Signals
Signal
Signal
Table 5–8
CPRI MegaCore function. The CPRI MII interface is enabled if you turn off Include
MAC block in the CPRI parameter editor. The CPRI MII interface signals are available
only if you enable the CPRI MII interface. For information about the MII handshaking
protocol implementation, refer to
Table 5–8
Table 5–9
you exclude the MAC block from the CPRI MegaCore function.
Output
Output
Output
Output
Output
Output
Input
Input
Direction
Direction
and
lists the CPRI MII interface receiver signals.
lists the CPRI MII interface transmitter signals. These signals are available if
Table 5–9
Clocks the MII receiver interface. The cpri_clkout clock drives this signal.
Ethernet write signal. Indicates the presence of a new K nibble or data value on
cpri_mii_rxd[3:0]. This signal is asserted during the first cpri_mii_rxclk
cycle in which the K nibble or a new data value appears on cpri_mii_rxd[3:0].
Ethernet receive data valid. Indicates the presence of valid data or initial K nibble on
cpri_mii_rxd[3:0].
Ethernet receive error. Indicates that the CPRI link is not initialized, and therefore
an error might be present in the frame being transferred to the external Ethernet
block. This signal is deasserted at reset, and asserted after reset until the CPRI
MegaCore function achieves frame synchronization.
Ethernet receive nibble data. Data bus for data from the CPRI MegaCore function to
the external Ethernet block. All bits are deasserted during reset, and all bits are
asserted after reset until the CPRI MegaCore function achieves frame
synchronization.
Clocks the MII transmitter interface. The cpri_clkout clock drives this signal.
Valid signal from the external Ethernet block, indicating the presence of valid data
on cpri_mii_txd[3:0]. This signal is also asserted while the CPRI MII interface
transmitter block inserts J and K nibbles in the data stream to form the
start-of-packet symbol. This signal is typically asserted one cycle after
cpri_mii_txrd is asserted. After that first cycle following the assertion of
cpri_mii_txrd, if cpri_mii_txen is not yet asserted, the CPRI MII transmitter module
inserts Idle cycles until the first cycle in which cpri_mii_txen is asserted. If
cpri_mii_txen is asserted and subsequently deasserted while cpri_mii_txrd
remains asserted, the CPRI MII transmitter module inserts the end-of-packet
sequence.
Ethernet transmit coding error. When this signal is asserted, the CPRI MegaCore
function inserts an Ethernet HALT symbol in the data it passes to the CPRI link.
list the signals used by the CPRI MII interface module of the
“MII Interface” on page
Description
Description
4–4.
December 2010 Altera Corporation
CPRI MII Interface Signals
Chapter 5: Signals