IP-CPRI Altera, IP-CPRI Datasheet - Page 119

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Software Interface
HDLC Registers
Table 6–63. ETH_CNT_RX_FRAME—Ethernet Receiver Module Frame Counter—Offset: 0x248
Table 6–64. ETH_CNT_TX_FRAME—Ethernet Transmitter Module Frame Counter—Offset: 0x24C
HDLC Registers
Table 6–65. CPRI HDLC Registers Memory Map
Table 6–66. HDLC_RX_STATUS—HDLC Receiver Module Status—Offset: 0x300 (Part 1 of 2)
December 2010 Altera Corporation
eth_cnt_rx_frame
eth_cnt_tx_frame
0x300
0x304
0x308
0x30C
0x310
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
0x330
0x334
RSRV
rx_ready_block
rx_ready_end
Address
Field
Field
Field
This section lists the HDLC registers.
HDLC registers.
CPRI MegaCore function.
[31:7] UR0
[6]
[5]
Bits
HDLC_RX_STATUS
HDLC_TX_STATUS
HDLC_CONFIG_1
HDLC_CONFIG_2
HDLC_RX_CONTROL
HDLC_RX_DATA
HDLC_RX_DATA_WAIT
HDLC_TX_CONTROL
HDLC_TX_DATA
HDLC_TX_DATA_WAIT
HDLC_RX_EX_STATUS
HDLC_CONFIG_3
HDLC_CNT_RX_FRAME
HDLC_CNT_TX_FRAME
RO
RO
[31:0]
[31:0]
Access
Bits
Bits
Name
Reserved.
Indicates that an eight-word block of HDLC data is available in the
HDLC Rx buffer to be transmitted on the HDLC channel.
Indicates the end-of-packet (EOP) is available in the HDLC Rx buffer,
ready to be transmitted on the HDLC channel.
RO
RO
Access
Access
Table 6–66
Number of frames received from the CPRI receiver.
Number of frame transmitted to the CPRI transmitter.
through
Table 6–79
HDLC Receiver Module Status
HDLC Transmitter Module Status
HDLC Feature Configuration 1
HDLC Feature Configuration 2
HDLC Rx Control
HDLC Rx Data
HDLC Rx Data With Wait-State Insertion
HDLC Tx Control
HDLC Tx Data
HDLC Tx Data With Wait-State Insertion
HDLC Rx Additional Status
HDLC Feature Configuration 3
HDLC Receiver Module Frame Counter
HDLC Transmitter Module Frame Counter
Table 6–65
Function
Function
Function
describe the HDLC registers in the
provides a memory map for the
Expanded Name
CPRI MegaCore Function User Guide
32'h0
32'h0
Default
Default
25'h0
1’h0
1’h0
Default
6–23