IP-CPRI Altera, IP-CPRI Datasheet - Page 88

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–8
Table 5–10. CPRI MAP Receiver Interface Signals (Part 2 of 2)
CPRI MegaCore Function User Guide
map{23…0}_rx_valid
map{23…0}_rx_resync
map{23…0}_rx_status_data[2:0]
Signal
Direction
Output
Input
Output
Valid signal for each antenna-carrier interface in FIFO mode. This
signal is asserted when the MAP_N Rx buffer exceeds the
threshold level in the map_rx_ready_thr field of the
CPRI_MAP_RX_READY_THR register. Although each data channel
has its own mapN_rx_valid signal, all data channels use the
same map_rx_ready_thr threshold value. This signal qualifies
all the other output signals of the CPRI MAP receiver interface.
On every rising edge of the clock at which mapN_rx_valid is
high, mapN_rx_data can be sampled.
Resynchronization signal for use in synchronous buffer mode.
When this signal is asserted, the read pointer of the MAP_N Rx
buffer is reset to zero. When the map_rx_sync_mode bit in the
CPRI_MAP_CONFIG register is set to 1, the MAP receiver
interface is in synchronous buffer mode. This signal is
synchronous to the
This vector contains the following status bits:
[2]
[1]
[0]
cpri_map_rx_overflow: Rx FIFO overflow indicator for
this antenna-carrier interface. This signal is synchronous
to the cpri_clkout clock, and is asserted following a
write to a full buffer. This signal reflects the value in the
appropriate bit of the buffer_rx_overflow field of the
CPRI_IQ_RX_BUF_STATUS register
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cpri_map_rx_underflow: Rx FIFO underflow indicator
for this antenna-carrier interface. This signal is
synchronous to the cpri_clkout clock, and is asserted
following a read from an empty buffer. This signal reflects
the value in the appropriate bit of the
buffer_rx_underflow field of the
CPRI_IQ_RX_BUF_STATUS register
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cpri_map_rx_en: Indicates that this antenna-carrier
interface is enabled. The value is determined in the
CPRI_IQ_RX_BUF_CONTROL register. Use this signal to
disable external logic for inactive AxC interfaces and to
map interface clock gating to save power.
6–18).
6–18).
mapN_rx_clk clock.
Description
December 2010 Altera Corporation
CPRI MAP Interface Signals
(Table 6–46 on
(Table 6–46 on
Chapter 5: Signals