IP-CPRI Altera, IP-CPRI Datasheet - Page 74

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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CPRI MegaCore Function User Guide
Ethernet Receiver
Software can set the tx_discard bit in the ETH_TX_CONTROL register, which in turn
causes the tx_abort bit in the ETH_TX_STATUS register to be set. The Ethernet
transmitter module can set the tx_abort bit directly.
Interrupts
Software can enable interrupts by setting bits in the ETH_CONFIG_1 register. The
intr_en bit is the Ethernet global interrupt enable and intr_tx_en is the Ethernet Tx
interrupt enable. If both of these two bits are set, software can use the status in the
ETH_TX_STATUS register to generate interrupts. For example, using the tx_ready_block
bit to generate an interrupt ensures that the CPU is interrupted only when a full 32-bit
packet of data can be written to the Ethernet Tx buffer.
The Ethernet receiver module receives Ethernet data from the CPRI link by reading it
from the Ethernet Rx buffer through an Ethernet register.
This section describes how the Ethernet receiver module performs MAC address
filtering according to the ETH_CONFIG_1, ETH_ADDR_LSB, and ETH_ADDR_MSB registers,
provides status information to the CPU interface in the ETH_RX_STATUS register, and
allows the CPU interface to insert wait states in the Ethernet channel.
For additional information about the Ethernet receiver registers, refer to
Software
MAC Address Filtering
To disable MAC address checking, set the mac_check bit of the ETH_CONFIG_1 register.
If the mac_check bit is set, the Ethernet receiver accepts all received packets.
All CPRI MegaCore function MAC address filters assume the MAC destination
address is in the first six bytes of the fast C&M data in the CPRI hyperframe. If the
MAC destination address is located elsewhere in the fast C&M data, you must set the
mac_check bit.
You can enable the following three MAC address filters:
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■
■
Unicast filtering: Check that the destination MAC address is the address specified
in the ETH_ADDR_LSB and ETH_ADDR_MSB registers. If the mac_check bit is not set, this
filter is enabled.
Multicast filtering: If the least significant bit of the first destination MAC address
byte, the group address bit, is set to 1, use the ETH_HASH_TABLE register to
determine whether to accept this destination MAC address. Because the hash
algorithm might not filter the destination address as intended, you must
implement full address validation in software if you enable multicast filtering. To
enable multicast filtering, set the multicast_flt_en bit of the ETH_CONFIG_1
register.
Broadcast filtering: Accept all packets with destination MAC address
0xFFFFFFFFFFFF, the Ethernet broadcast address. To enable broadcast filtering, set
the broadcast_en bit of the ETH_CONFIG_1 register.
Interface.
Data Link Layer for Fast Control and Management Channel (Ethernet)
December 2010 Altera Corporation
Chapter 4: Functional Description
Chapter 6,