IP-CPRI Altera, IP-CPRI Datasheet - Page 63

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Delay Measurement
Delay Measurement
December 2010 Altera Corporation
Delay Requirements
The cpri_tx_aux_data and cpri_tx_aux_mask signals are fields of the
aux_tx_mask_data bus. The other signals described in the preceding list are fields of
the aux_tx_status_data bus. For additional information about the AUX transmitter
signals, refer to
For system configuration and correct synchronization, the CPRI MegaCore function
must meet the CPRI V4.1 Specification measurement and delay requirements. The
CPRI MegaCore function makes the current Rx delay measurement values available
in the CPRI_RX_DELAY and CPRI_EX_DELAY_STATUS delay registers, and makes the
round-trip delay measurement available in the CPRI_ROUND_DELAY register. In
addition, the MegaCore function allows you to specify settings that control the degree
of delay accuracy in the status registers, by programming the CPRI_RX_DELAY_CTRL
and CPRI_EX_DELAY_CONFIG registers.
The following sections describe the delay requirements and how you can use these
registers to ensure that your application conforms to the CPRI V4.1 Specification
delay requirements.
CPRI V4.1 Specification requirements R-17, R-18, and R-18A address jitter and
frequency accuracy in the RE core clock for radio transmission. The relevant clock
synchronization is performed using an external clean-up PLL that is not included in
the CPRI MegaCore function.
The CPRI MegaCore function complies with CPRI V4.1 Specification requirements
R-19, R-20, R-20A, R-21, and R-21A.
CPRI V4.1 Specification requirement R-20A addresses the maximum allowed delay in
switching between receiving and transmitting on the AxC interface. Because the CPRI
MegaCore function provides duplex communication on the AxC interfaces, this
switch requires only the programming of the relevant AxC interface Tx or Rx enable
bit in the CPRI_IQ_TX_BUF_CONTROL or CPRI_IQ_RX_BUF_CONTROL register, and no delay
calculation is required.
Requirement R-19 specifies that the link delay accuracy for the downlink between the
synchronization master SAP and the synchronization slave SAP, excluding the cable
length, be within ±8.138 ns. Requirements R-20 and R-21 extrapolate this requirement
to single-hop round-trip delay accuracy. R-20 requires that the accuracy of the
round-trip delay, excluding cables, be within ±16.276 ns, and R-21 requires that the
round-trip cable delay measurement accuracy be within the same range. Requirement
R-21A extrapolates this requirement further, to multi-hop round-trip delay accuracy.
In calculating these delays, Altera assumes that the downlink and uplink cable delays
have the same duration.
Table 5–13 on page
5–12.
CPRI MegaCore Function User Guide
4–39