IP-CPRI Altera, IP-CPRI Datasheet - Page 89

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Signals
CPRI MAP Interface Signals
Table 5–11. CPRI MAP Transmitter Interface Signals (Part 1 of 2)
December 2010 Altera Corporation
map{23…0}_tx_clk
map{23…0}_tx_reset
map{23…0}_tx_valid
map{23…0}_tx_data[31:0]
map{23…0}_tx_ready
map{23…0}_tx_resync
CPRI MAP Transmitter Signals
Signal
Table 5–11
lists the CPRI MAP transmitter interface signals.
Input
Input
Input
Input
Output
Input
Direction
Clock signal for each antenna-carrier interface.
Reset signal for each antenna-carrier interface. This reset is associated
with the mapN_tx_clk clock.
mapN_tx_reset can be asserted asynchronously, but must stay
asserted at least one mapN_tx_clk cycle and must be deasserted
synchronously with mapN_tx_clk. Refer to
for a circuit that shows how to enforce synchronous deassertion of a
reset signal.
Write-valid signal for each antenna-carrier interface. This signal
qualifies all the other Avalon-ST input signals of the CPRI MAP
transmitter interface. On every rising edge of the clock at which
mapN_tx_valid is high, data is sampled by the MegaCore function. In
synchronous buffer mode, the application must assert this signal
immediately after it asserts the resynchronization signal.
32-bit write data from each antenna-carrier interface. Data is valid one
mapN_tx_clk clock cycle after the write-valid bit is asserted. Bits
[15:0] are the I component of the IQ sample. Bits [31:16] are the Q
component of the IQ sample.
Ready signal for each antenna-carrier interface. In FIFO mode, the ready
signal is asserted when the MAP_N Tx buffer falls below the threshold
level in the map_tx_ready_thr field of the CPRI_MAP_TX_READY_THR
register. Although each data channel has its own mapN_tx_ready
signal, all data channels use the same map_tx_ready_thr threshold
value. Indicates that the MegaCore function is ready to receive data on
the data channel in the current clock cycle. Asserted by the Avalon-ST
sink to mark ready cycles, which are the cycles in which transfers can
take place. If ready is asserted on cycle N, the cycle
(N+READY_LATENCY) is a ready cycle.
In the CPRI MAP transmitter interface, READY_LATENCY is equal to 0,
so the cycle on which mapN_tx_ready is asserted is the ready cycle.
Resynchronization signal for use in synchronous buffer mode. When
the map_tx_sync_mode bit in the CPRI_MAP_CONFIG register is set to
1, the MAP transmitter interface is in synchronous buffer mode. This
signal is synchronous to the
mapN_tx_clk clock.
Description
CPRI MegaCore Function User Guide
Figure 4–8 on page 4–14
5–9