IP-CPRI Altera, IP-CPRI Datasheet - Page 94
IP-CPRI
Manufacturer Part Number
IP-CPRI
Description
IP CORE - Common Public Radio Interface (CPRI)
Manufacturer
Altera
Specifications of IP-CPRI
Software Application
IP CORE, Interface And Protocols, HIGH SPEED
Supported Families
Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 94 of 142
- Download datasheet (3Mb)
5–14
Table 5–14. Extended Rx Status Signals
CPRI MegaCore Function User Guide
extended_rx_status_data
[11:0]
Extended Rx Status Signals
Signal
Table 5–14
report on the status of the CPRI receiver frame synchronization machine.
lists the signals on the extended Rx status interface. All of these signals
Output
Direction
[11]
[10:8]
[7]
[6]
[5]
[4:2]
[1:0]
Bits
cpri_rx_los: CPRI receiver LOS indication (active high). This
bit reflects the value in the rx_los field of the CPRI_INTR
register
cpri_rx_lcv: Current CPRI receiver 8B/10B line code violation
count in current clock cycle. This information enables CPRI link
debug when the control word does not appear or is malformed.
cpri_rx_hfn_state: When set, indicates that hyperframe
synchronization (HFN) has been achieved in CPRI receiver frame
synchronization.
cpri_rx_bfn_state: When set, indicates that basic frame
synchronization (BFN) has been achieved in CPRI receiver frame
synchronization.
cpri_rx_freq_alarm: Frequency alarm. When set, indicates a
frequency difference greater than four clock cycles between
cpri_clkout and the recovered received clock from the CPRI
receiver interface.
cpri_rx_cnt_sync: CPRI receiver frame synchronization state
machine state. Tracks the number of K28.5 symbols received so
far toward the five required by the receiver frame
synchronization machine to reach the XSYNC state.
cpri_rx_state: Indicates the state of the CPRI receiver frame
synchronization state machine. The following values are defined:
In the HFNSYNC state, Rx synchronization has been achieved,
except for initialization of the hyperframe and basic frame
numbers. You must wait for
cpri_rx_bfn_state to have value 1, indicating that the
hyperframe number and basic frame number are initialized.
00 - LOS state
01 - XACQ state
10 - XSYNC state
11 - HFNSYNC state
(Table 6–4 on page
Description
6–2).
cpri_rx_hfn_state and
December 2010 Altera Corporation
Auxiliary Interface Signals
Chapter 5: Signals
Related parts for IP-CPRI
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IPT-C2H-NIOS
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE - XAUI PHY
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE - RLDRAM II Controller
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE - QDRII SRAM Controller
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
MODULE, TX/RX, W/ PSU, IP-LINK
Manufacturer:
TOPCO SNT
Datasheet:
Part Number:
Description:
I2C Controller FPGA IP Core
Manufacturer:
SYSTEM LEVEL SOLUTIONS
Part Number:
Description:
IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP NIOS II MEGACORE
Manufacturer:
Altera
Datasheet: