IP-CPRI Altera, IP-CPRI Datasheet - Page 42

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–18
Table 4–3. Transceiver Datapath Width and rx_clkout Divider for Input to Rx Elastic Buffer
CPRI MegaCore Function User Guide
614.4
Greater than 614.4
CPRI Line Rate
Low-level Interface Receiver
(Mbps)
The receiver in the low-level interface receives the input from the CPRI interface, and
performs the following tasks:
■
■
■
■
■
■
High-Speed Transceiver
The transceiver is an embedded ALTGX megafunction in the Arria II GX, Arria II GZ,
Cyclone IV GX, or Stratix IV GX device. The transceiver receiver implements 8B/10B
decoding and the deterministic latency protocol. The deterministic latency protocol is
designed to meet the 16.276 ns round-trip delay measurement accuracy requirements
R21 and R21A of the CPRI specification.
Rx Elastic Buffer
The low-level interface receiver converts data from the transceiver clock domain to
the main CPRI MegaCore function clock domain using a synchronization FIFO called
the Rx elastic buffer. The Rx elastic buffer data output is clocked with the cpri_clkout
clock. The Rx elastic buffer data input is synchronous with the rx_clkout clock from
the transceiver, divided by one, two, or four, depending on the datapath width in the
transceiver. The width of an Rx elastic buffer entry is 32 bits, and the rx_clkout clock
is divided with the transceiver data conversion to 32-bit words. For details, refer to
“Clock Diagrams for the CPRI MegaCore Function” on page
Table 4–3
CPRI data rates.
The depth of the Rx elastic buffer is 64 in REC configurations and 16 in RE
configurations. For most systems, the default Rx elastic buffer depth is adequate to
handle dispersion, jitter, and wander that can occur on the link while the system is
running.
Converts the data to the main clock domain
Performs CPRI frame detection, supporting auto-rate negotiation
Separates data and control words
Optionally descrambles data at 4195.2 Mbps and 6144.0 Mbps CPRI line rates
Separates data for the CPRI MAP interface block, the AUX module, the Ethernet
MAC block or the MII module, and the HDLC module
Detects Loss of Signal (LOS), Loss of Frame (LOF), Remote Alarm Indication
(RAI), and Service Access Point (SAP) Defect Indication (SDI) errors
All
Arria II GX, Cyclone IV GX
Arria II GZ, Stratix IV GX
shows the rx_clkout clock divider for the different device families and
Device Family
Transceiver Datapath Width
(Bits)
16
32
8
December 2010 Altera Corporation
Chapter 4: Functional Description
4–6.
rx_clkout Divider
4
2
1
Physical Layer