IP-CPRI Altera, IP-CPRI Datasheet - Page 33

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Clocking and Reset Structure
Figure 4–4. CPRI MegaCore Function Slave Clocking in Arria II GZ and Stratix IV GX Devices
Note to
(1) The clk_ex_delay input clock can be driven by a cleanup PLL. However, it can also be driven by other clock logic that provides the correct M/N
December 2010 Altera Corporation
ratio for the accuracy required by the application. Refer to
gxb_txdataout
gxb_rxdatain
Figure
4–4:
gxb_refclk
rx_cruclk
Figure 4–4
RE slave with CPRI line rate greater than 0.6144 Gbps in an Arria II GZ or
Stratix IV GX device.
ALTGX
CDR
pll_clkout
shows the clock diagram for a CPRI MegaCore function configured as an
rx_clkout
tx_clkout
pll_inclk
Clean-Up PLL
data
gxb_pll_inclk
32
“Extended Rx Delay Measurement” on page
clk_ex_delay
cpri_clkout
32
Sync Buffer
Rx Elastic
CPRI RX
CPRI TX
(1)
clk
clk
cpri_tx_aux_data
32
32
cpri_rx_aux_data
32
32
Ethernet MAC
data
HDLC
clk
clk
CPRI MegaCore Function
data
4–42.
Interface
CPRI Tx
CPRI Rx
Interface
FIFO
FIFO
CPRI MegaCore Function User Guide
MAP
MAP
clk
MII Interface
Interface
CPU
mapXX_tx_data
mapXX_tx_clk
mapXX_rx_clk
mapXX_rx_data
cpu_clk
cpri_mii_txclk
cpri_mii_rxclk
cpu_writedata
cpu_readdata
4–9