IP-CPRI Altera, IP-CPRI Datasheet - Page 38

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–14
CPRI MegaCore Function User Guide
You can assert all reset signals asynchronously to any clock. However, each reset
signal must be asserted for at least one full clock period of a specific clock, and be
deasserted synchronously to the rising edge of that clock. For example, the CPU
interface reset signal, cpu_reset, must be deasserted on the rising edge of cpu_clk.
Table 4–2
Table 4–2. Reset Signals and Corresponding Clock Domains
You must implement logic to ensure the minimal hold time and synchronous
deassertion of each reset input signal to the CPRI MegaCore function.
shows a circuit that ensures these conditions for one reset signal.
Figure 4–8. Circuit to Ensure Synchronous Deassertion of Reset Signal
For more information about the requirements for reset signals, refer to
Signals.
Reset Controller
The CPRI MegaCore function has a dedicated reset control module to handle the
specific requirements of the high-speed transceiver module. This module generates
the recommended reset sequence for the transceiver. The reset signal controls the
reset control module.
Reset Signal
reset
gxb_powerdown
reset_ex_delay
config_reset
cpu_reset
mapN_rx_reset
mapN_tx_reset
shows the reset signals and their corresponding clock domains.
clk
rst
V
Clock Domain
reconfig_clk
clk_ex_delay
cpri_clkout
cpu_clk
mapN_rx_clk
mapN_tx_clk
CC
D
rst
—
Q
D
rst
Description
Resets the CPRI interface
Powers down and resets the high-speed
transceiver block. For setup and hold times,
refer to the relevant device handbook.
Resets the extended delay measurement block
Resets the registers to their default values
Resets the CPU interface
Resets the MAP Channel N receiver block
Resets the MAP Channel N transmitter block
Q
reset
December 2010 Altera Corporation
Chapter 4: Functional Description
MegaCore
Function
CPRI
Clocking and Reset Structure
Figure 4–8
Chapter 5,