IP-CPRI Altera, IP-CPRI Datasheet - Page 129

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 7: Testbenches
Reset, Frame Synchronization, and Initialization
Reset, Frame Synchronization, and Initialization
Table 7–3. Testbench Registers
December 2010 Altera Corporation
0x0008
0x0104
0x0100
Register
Address
CPRI_CONFIG
CPRI_MAP_CNT_CONFIG
CPRI_MAP_CONFIG
Register Name
■
All testbenches perform self-checking and output the pass/fail results to your
Modelsim session. In addition, each testbench includes simulator files that allow you
to observe the signals in and out of the AUX interface, antenna-carrier interfaces, and
MII interface if relevant.
The reset sequence is simple—all of the reset signals for the DUT except
gxb_powerdown and reset_ex_delay are asserted at the beginning of the simulation,
are kept high for 500 ns, and are then deasserted. The following reset signals are
asserted:
■
■
■
■
■
When frame synchronization completes, the value on the cpri_rx_state output port
(bits [1:0] of the extended_rx_status_data bus) is 0x3 and the value on the
cpri_rx_cnt_sync port (bits [4:2] of the extended_rx_status_data bus) is 0x2.
Following the appearance of these values, the value of the cpri_rx_hfn_state output
signal transitions to value 1, and then value of the cpri_rx_bfn_state output signal
transitions to value 1. When these values appear in the waveform display, the CPRI
link is up and ready to receive and send data.
Next, basic programming of the internal registers is performed in the DUT to allow
CPRI communication.
tb_altera_cpri and tb_altera_cpri_mii DUTs. For a full description of each register,
refer to
If relevant, sends a predetermined data sequence to the MII interface, and checks
that the data appears as expected on the outgoing MII interface after loopback
through the CPRI link (tb_altera_cpri_mii and tb_altera_cpri_mii_noiq only).
This test also checks the MII interface handling of the input error indication signal.
The signal is asserted during parts of the incoming data sequence, and the
expected output data reflects the correct handling of data in this case.
reset
cpu_reset
config_reset
mapN_tx_reset for N={1...3}
mapN_rx_reset for N={1...3}
Chapter 6, Software
Enable CPRI control word insertion, set the CPRI MegaCore to
use master clocking mode, set loop_mode to No internal
loopback, and enable transmission on the CPRI link.
Set number of active data channels to 3 and the oversampling
factor to 1.
Set map_mode to basic mapping scheme, set MAP transmitter
and receiver synchronization mode to non-FIFO mode, and use
16-bit sample width.
Table 7–3
Interface.
shows the registers that are programmed in the
Description
CPRI MegaCore Function User Guide
0x00000021
0x00000301
0x0000000C
Value
7–5