IP-CPRI Altera, IP-CPRI Datasheet - Page 57

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Auxiliary Interfaces
Auxiliary Interfaces
December 2010 Altera Corporation
PRBS Generation and Validation
On the CPRI side of the mapN Tx buffer, the CPRI MAP transmitter interface reads
data from the mapN Tx buffer and sends it to the CPRI transmitter interface. The
offset programmed in the CPRI_MAP_OFFSET_TX register tells the CPRI MAP
transmitter interface when to reset the read pointer of the mapN Tx buffer and start
transfering data from the buffer to the CPRI transmitter interface. The K counter is
reset to zero at the same time, so that it advances from zero with the transfer of the
data to the CPRI transmitter interface, tracking the packing of the AxC container block
contents into the CPRI frame.
Because the mapN Tx buffer should not be read before it is written, the offset specified
in the CPRI_START_OFFSET_TX register must precede the offset specified in the
CPRI_MAP_OFFSET_TX register. The CPRI MegaCore function informs you of buffer
overflow and underflow (in the CPRI_IQ_TX_BUF_STATUS register described in
Table 6–47 on page 6–18
described in
Altera recommends that you implement a separate tracking protocol to ensure you do
not overflow or underflow the mapN Tx buffer.
You set the values in the CPRI_START_OFFSET_TX and CPRI_MAP_OFFSET_TX registers to
provide the correct timing to compensate for delays through the CPRI MegaCore
function. For information about delays in the Tx path through the IP core, refer to
Path Delay” on page
The CPRI MegaCore function supports generation and validation of several
predetermined pseudo-random binary sequences (PRBS) for antenna-carrier interface
testing. The value in the prbs_mode field of the CPRI_PRBS_CONFIG register specifies
whether the CPRI MAP interface module is in data mode or in internal loopback
mode, and the generated pattern for loopback mode. The value applies to all AxC
interfaces. The following prbs_mode values are available:
■
■
■
The value 11 is reserved.
The CPRI_PRBS_STATUS register records the PRBS error detection status for each AxC
interface.
The CPRI auxiliary interfaces enable multi-hop routing applications and provide
timing reference information for transmitted and received frames. The AUX Receiver
and AUX Transmitter interfaces are implemented as separate Avalon-ST interfaces.
The AUX transmitter receives data to be transmitted on the outgoing CPRI link, and
the AUX receiver transmits data received from the incoming CPRI link.
00: Indicates that data samples, and not a PRBS test pattern, are expected on the
AxC interfaces. This value indicates the CPRI MAP interface module is not in
internal loopback testing mode.
01: Indicates an incremental counter sequence, starting at zero at the start of a
10 ms radio frame, and counting to 255 before rolling over. The counter value
appears in both halves of the 32-bit data word.
10: Indicates an inverted 2
halves of the 32-bit data word.
Table 5–11 on page
4–46.
and as reported in the mapN_tx_status_data output vector
23
– 1 PRBS sequence. Each pattern appears in both
5–9), but it does not prevent them from occurring.
CPRI MegaCore Function User Guide
“Tx
4–33