FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 106

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

UART Power Management
Direct power management is controlled by
CR22. Refer to CR22 for more information.
Auto Power Management is enabled by CR23-
B4 and B5.
following auto power management operations:
1.
2.
Note:
Exit Auto Powerdown
The transmitter exits powerdown on a write to
the XMIT buffer.
powerdown when RXDx changes state.
The transmitter enters auto powerdown
when the transmit buffer and shift register
are empty.
The receiver enters powerdown when the
following conditions are all met:
a.
b.
Receive FIFO is empty
The receiver is waiting for a start bit.
While in powerdown the Ring Indicator
interrupt is still valid and transitions
when the RI input changes.
When set, these bits allow the
The receiver exits auto
106
Parallel Port
Direct power management is controlled by
CR22. Refer to CR22 for more information.
Auto Power Management is enabled by CR23-
B3. When set, this bit allows the ECP or EPP
logical parallel port blocks to be placed into
powerdown when not being used.
The EPP logic is in powerdown under any of the
following conditions:
1.
2.
The ECP logic is in powerdown under any of the
following conditions:
1.
2
Exit Auto Powerdown
The parallel port logic can change powerdown
modes when the ECP mode is changed through
the ecr register or when the parallel port mode is
changed through the configuration registers.
EPP is not enabled in the configuration
registers.
EPP is not selected through ecr while in
ECP mode.
ECP is not enabled in the configuration
registers.
SPP, PS/2 Parallel port or EPP mode is
selected through ecr while in ECP mode.