FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 167

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

There are two of the following registers in the configuration data space, one for each drive.
FDD0 - 0xF4
FDD1 - 0xF5
PTS
DTx
DRTx
(1) DENSEL, DRATE1 and DRATE0 map onto three output pins DRVDEN0 and DRVDEN1.
IDE Controller Modifications
FDC/HDC split register eliminated. Typical system design implementations put the FDC registers
the registers used by the FDC and the IDE shows an overlap at I/O address 0x3f6 and 0x3f7.
System I/O accesses to 0x3f6 result in no contention as 0x3f6 is undefined for the FDC. Sytem
I/O writes to 0x3f7 result in no contention as the IDE interface does not perform writes to this
register. The only contention would normally occur when the system issues I/O reads to 0x3f7.
THE FDC37C667, HOWEVER, WILL NOT DECODE IDE ACCESS TO 0x3f7 (see section 3b,
Logical Device I/O Map for IDE devices). The FDC, when configured for the AT mode, drives bit
D7 only. When configured for PS/2 or Model 30 mode the FDC will drive the entire byte.
D7
at I/O Base address 0x3f0 and the IDE Misc AT registers at I/O Base address 0x3f6. Looking at
0
DT0
0
0
1
1
= 0 Use Precompensation
= 1 No Precompensation
= Drive Type select
= Data Rate Table select
DT1
0
1
0
1
PTS
D6
DRVDEN0 (1)
nDENSEL
DENSEL
DRATE1
DRATE0
D5
0
DRT1
D4
DRVDEN1 (1)
167
DRATE0
DRATE0
DRATE0
DRATE1
DRT0
D3
4/2/1 MB 3.5"
2/1 MB 5.25" FDDS
2/1.6/1 MB 3.5" (3-MODE)
D2
0
DRIVE TYPE
DT0
D1
DT1
D0