FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 196

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the
peak 500Kbytes/sec allowed in the forward
direction using DMA. The state machine does
not examine and begins the next transfer based
on Busy. Refer to Figure 20.
ECP Parallel Port Timing
The timing is designed to allow operation at
approximately 2.0 Mbytes/sec over a 15ft cable.
will increase.
Forward-Idle
When the host has no data to send it keeps
HostClk () high and the peripheral will leave
PeriphClk (Busy) low.
Forward Data Transfer Phase
The interface transfers data and commands
from the host to the peripheral using an inter-
locked PeriphAck and HostClk. The peripheral
may indicate its desire to send data to the host
by asserting .
The Forward Data Transfer Phase may be
entered from the Forward-Idle Phase. While in
the
asynchronously assert the () to request that the
channel be reversed. When the peripheral is not
busy it sets PeriphAck (Busy) low. The host then
sets HostClk () low when it is prepared to send
data. The data must be stable for the specified
setup time prior to the falling edge of HostClk.
The peripheral then sets PeriphAck (Busy) high
to acknowledge the handshake. The host then
sets HostClk () high. The peripheral
accepts the data and sets PeriphAck (Busy)
low, completing the transfer. This sequence is
shown in Figure 21.
If a shorter cable is used then the bandwidth
Forward
Phase
the
peripheral
ECP PARALLEL PORT TIMING
then
may
196
The timing is designed to provide 3 cable
round-trip times for data setup if Data is driven
simultaneously with HostClk ().
Reverse-Idle Phase
The peripheral has no data to send and keeps
PeriphClk high. The host is idle and keeps
HostAck low.
Reverse Data Transfer Phase
The interface transfers data and commands
from the peripheral to the host using an inter-
locked HostAck and PeriphClk.
The Reverse Data Transfer Phase may be en-
tered from the Reverse-Idle Phase.
previous byte has beed accepted the host sets
HostAck () low. The peripheral then sets
PeriphClk () low when it has data to send. The
data must be stable for the specified setup time
prior to the falling edge of PeriphClk. When the
host is ready it to accept a byte it sets. HostAck
() high to acknowledge the handshake. The
peripheral then sets PeriphClk () high. After the
host has accepted the data it sets HostAck ()
low, completing the transfer. This sequence is
shown in Figure 22.
Output Drivers
To facilitate higher performance data transfer,
the use of balanced CMOS active drivers for
critical
PeriphAck, PeriphClk) are used ECP Mode.
Because the use of active drivers can present
compatibility
(the control signals, by tradition, are specified
changed from open-collector to totem-pole. The
timing for the
specified in
Capabilities
as open-collector), the drivers are dynamically
signals
problems in Compatible Mode
Port
the
dynamic driver change
(Data,
IEEE
Protocol
HostAck,
1284 Extended
and
After the
HostClk,
ISA
is